Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.

Abstract: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, an epitaxial regrowth layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is over a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is over a backside of the source epitaxial structure and a backside of the drain epitaxial structure. The epitaxial regrowth layer is on the backside of a first one of the source epitaxial structure and the drain epitaxial structure. The backside via extends through the backside dielectric layer and overlaps the epitaxial regrowth layer.

Abstract: Embodiments of the present disclosure provide a method for forming backside metal contacts with reduced Cgd and increased speed. Particularly, source/drain features on the drain side, or source/drain features without backside metal contact, are recessed from the backside to the level of the inner spacer to reduce Cgd. Some embodiments of the present disclosure use a sacrificial liner to protect backside alignment feature during backside processing, thus, preventing shape erosion of metal conducts and improving device performance.

Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench; depositing a first metal oxide layer over the interfacial layer; removing the first metal oxide layer from the pFET structure; depositing a ferroelectric layer in each gate trench; depositing a second metal oxide layer over the ferroelectric layer; removing the second metal oxide layer from the nFET structure; and depositing a gate electrode in each gate trench.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers and a first source/drain epitaxial feature in contact with the plurality of semiconductor layers. The first source/drain epitaxial feature includes a bottom portion having substantially straight sidewalls. The structure further includes a spacer having a gate spacer portion and one or more source/drain spacer portions. Each source/drain spacer portion has a first height, and a source/drain spacer portion of the one or more source/drain spacer portions is in contact with one of the substantially straight sidewalls of the first source/drain epitaxial feature. The structure further includes a dielectric feature disposed adjacent one source/drain spacer portion of the one or more source/drain spacer portion. The dielectric has a second height substantially greater than the first height.

Abstract: In an embodiment, a device includes: a first nanostructure over a substrate, the first nanostructure including a channel region and a first lightly doped source/drain (LDD) region, the first LDD region adjacent the channel region; a first epitaxial source/drain region wrapped around four sides of the first LDD region; an interlayer dielectric (ILD) layer over the first epitaxial source/drain region; a source/drain contact extending through the ILD layer, the source/drain contact wrapped around four sides of the first epitaxial source/drain region; and a gate stack adjacent the source/drain contact and the first epitaxial source/drain region, the gate stack wrapped around four sides of the channel region.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first gate structure disposed over a first backside dielectric feature, a second gate structure disposed over a second backside dielectric feature, a gate cut feature extending continuously from between the first gate structure and the second gate structure to between the first backside dielectric feature and the second backside dielectric feature, and a liner disposed between the gate cut feature and the first backside dielectric feature and between the gate cut feature and the second backside dielectric feature.

Abstract: In an embodiment, a device includes: a power rail contact; an isolation region on the power rail contact; a first dielectric fin on the isolation region; a second dielectric fin adjacent the isolation region and the power rail contact; a first source/drain region on the second dielectric fin; and a source/drain contact between the first source/drain region and the first dielectric fin, the source/drain contact contacting a top surface of the first source/drain region, a side surface of the first source/drain region, and a top surface of the power rail contact.

Abstract: An IC structure includes a source epitaxial structure, a drain epitaxial structure, a first silicide region, a second silicide region, a source contact, a backside via rail, a drain contact, and a front-side interconnection structure. The first silicide region is on a front-side surface, a first sidewall of the source epitaxial structure, and a second sidewall of the source epitaxial structure. The second silicide region is on a front-side surface of the drain epitaxial structure. The source contact is in contact with the first silicide region and has a protrusion extending past a backside surface of the source epitaxial structure. The backside via rail is in contact with the protrusion of the source contact. The drain contact is in contact with the second silicide region. The front-side interconnection structure is on a front-side surface of the source contact and a front-side surface of the drain contact.

Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.

Abstract: A method of configuring a display device interface (DDI) detects a trigger signal, generated by a display device. If the trigger signal is associated with a power on event, a full configuration of the DDI is performed, including loading display device capability information provided by the display device into DDI configuration registers and setting one or more DDI configuration parameters accordingly. If the trigger signal is associated with resume event, rather than a power on event, a modified fast link resume operation may be performed to route the trigger signal to a controller configured to explicitly write display device capability information to the appropriate DDI configuration registers before setting the corresponding DDI configuration parameter accordingly. The DDI may include a re-timer, between the DDI source and sink, configured to snoop the explicit write transaction such that the re-timer configuration is also updated.

Abstract: Embodiments of the present disclosure provide a method for forming backside metal contacts with reduced Cgd and increased speed. Particularly, source/drain features on the drain side, or source/drain features without backside metal contact, are recessed from the backside to the level of the inner spacer to reduce Cgd. Some embodiments of the present disclosure use a sacrificial liner to protect backside alignment feature during backside processing, thus, preventing shape erosion of metal conducts and improving device performance.

Abstract: In an embodiment, a device includes: a first fin; a gate structure over the first fin; a first source/drain region adjacent the gate structure; an etch stop layer over the first source/drain region; a conductive line over the etch stop layer, the conductive line isolated from the first source/drain region by the etch stop layer, a top surface of the conductive line being coplanar with a top surface of the gate structure; and a power rail contact extending through the first fin, the power rail contact connected to the first source/drain region.

Abstract: A semiconductor device according to the present disclosure includes a vertical stack of channel members, a gate structure over and around the vertical stack of channel members, and a first source/drain feature and a second source/drain feature. Each of the vertical stack of channel members extends along a first direction between the first source/drain feature and the second source/drain feature. Each of the vertical stack of channel members is spaced apart from the first source/drain feature by a silicide feature.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a source region, a drain region, and a gate electrode layer disposed between the source region and the drain region. The gate electrode layer includes a first surface facing the source region, and the first surface includes an edge portion having a first height. The gate electrode layer further includes a second surface opposite the first surface and facing the drain region. The second surface includes an edge portion having a second height. The second height is different from the first height.

Abstract: A semiconductor device includes a first fin, a second fin, a first gate electrode having a first portion that at least partially wraps around an upper portion of the first fin and a second portion that at least partially wraps around an upper portion of the second fin, a second gate electrode having a portion that at least partially wraps around the upper portion of the first fin, and a gate-cut feature having a first portion in the first gate electrode between the first and second portions of the first gate electrode. The gate-cut feature is at least partially filled with one or more dielectric materials. In a direction of a longitudinal axis of the first fin, the gate-cut feature has a second portion extending to a sidewall of the second gate electrode.

Abstract: An IC structure includes a source epitaxial structure, a drain epitaxial structure, a first silicide region, a second silicide region, a source contact, a backside via rail, a drain contact, and a front-side interconnection structure. The first silicide region is on a front-side surface and a first sidewall of the source epitaxial structure. The second silicide region is on a front-side surface of the drain epitaxial structure. The source contact is in contact with the first silicide region and has a protrusion extending past a backside surface of the source epitaxial structure. The backside via rail is in contact with the protrusion of the source contact. The drain contact is in contact with the second silicide region. The front-side interconnection structure is on a front-side surface of the source contact and a front-side surface of the drain contact.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers and a first source/drain epitaxial feature in contact with the plurality of semiconductor layers. The first source/drain epitaxial feature includes a bottom portion having substantially straight sidewalls. The structure further includes a spacer having a gate spacer portion and one or more source/drain spacer portions. Each source/drain spacer portion has a first height, and a source/drain spacer portion of the one or more source/drain spacer portions is in contact with one of the substantially straight sidewalls of the first source/drain epitaxial feature. The structure further includes a dielectric feature disposed adjacent one source/drain spacer portion of the one or more source/drain spacer portion. The dielectric has a second height substantially greater than the first height.

Abstract: A device includes a first semiconductor strip protruding from a substrate, a second semiconductor strip protruding from the substrate, an isolation material surrounding the first semiconductor strip and the second semiconductor strip, a nanosheet structure over the first semiconductor strip, wherein the nanosheet structure is separated from the first semiconductor strip by a first gate structure including a gate electrode material, wherein the first gate structure partially surrounds the nanosheet structure, and a first semiconductor channel region and a semiconductor second channel region over the second semiconductor strip, wherein the first semiconductor channel region is separated from the second semiconductor channel region by a second gate structure including the gate electrode material, wherein the second gate structure extends on a top surface of the second semiconductor strip.

Abstract: A semiconductor device according to the present disclosure includes a vertical stack of channel members, a gate structure over and around the vertical stack of channel members, and a first source/drain feature and a second source/drain feature. Each of the vertical stack of channel members extends along a first direction between the first source/drain feature and the second source/drain feature. Each of the vertical stack of channel members is spaced apart from the first source/drain feature by a silicide feature.