Patents by Inventor Pei Yu Wang
Pei Yu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12389634Abstract: A semiconductor device including an embedded channel structure, a sidewall channel structure and a gate electrode structure is provided. The embedded channel structure is disposed on a substrate. The sidewall channel structure is disposed on the substrate, and located at a lateral side of the embedded channel structure. The gate electrode structure is disposed on the substrate, encircles the embedded channel structure and is located between the embedded channel structure and the sidewall channel structure.Type: GrantFiled: May 23, 2022Date of Patent: August 12, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Pei-Yu Wang
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Patent number: 12374624Abstract: In an embodiment, a device includes: a first fin; a gate structure over the first fin; a first source/drain region adjacent the gate structure; an etch stop layer over the first source/drain region; a conductive line over the etch stop layer, the conductive line isolated from the first source/drain region by the etch stop layer, a top surface of the conductive line being coplanar with a top surface of the gate structure; and a power rail contact extending through the first fin, the power rail contact connected to the first source/drain region.Type: GrantFiled: April 11, 2024Date of Patent: July 29, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pei-Yu Wang, Yu-Xuan Huang
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Patent number: 12376356Abstract: The present disclosure relates to a semiconductor device having a backside source/drain contact, and method for forming the device. The semiconductor device includes a source/drain feature having a top surface and a bottom surface, a first silicide layer formed in contact with the top surface of the source/drain feature, a first conductive feature formed on the first silicide layer, and a second conductive feature having a body portion and a first sidewall portion extending from the body portion, wherein the body portion is below the bottom surface of the source/drain feature, and the first sidewall portion is in contact with the first conductive feature.Type: GrantFiled: February 28, 2024Date of Patent: July 29, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Yuan Chen, Pei-Yu Wang, Huan-Chieh Su, Chih-Hao Wang
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Publication number: 20250234595Abstract: Inner spacers between a source/drain region of a nanostructure transistor and sacrificial nanostructure layers of the nanostructure transistor are removed prior to formation of a gate structure of the nanostructure transistor. The sacrificial nanostructure layers are removed, and then the inner spacers are removed. The sacrificial nanostructure layers are then replaced with the gate structure of the nanostructure transistor such that the gate structure and the source/drain region are spaced apart by air gaps that result from the removal of the inner spacers. The dielectric constant (or relative permittivity) of the air gaps between the source/drain region and the gate structure is less than the dielectric constant of the material of the inner spacers. The lesser dielectric constant of the air gaps reduces the amount of capacitance between the source/drain region and the gate structure.Type: ApplicationFiled: May 22, 2024Publication date: July 17, 2025Inventors: Hsien-Chih HUANG, Guang-Lin CHEN, Pei-Yu WANG, Chia-Hao YU, Kuo-Cheng CHIANG, Chih-Hao WANG
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Publication number: 20250226271Abstract: A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.Type: ApplicationFiled: March 25, 2025Publication date: July 10, 2025Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Tsung-Yu LIN, Pei-Yu WANG, Chung-Wei HSU
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Patent number: 12347690Abstract: A semiconductor device includes a first fin protruding upwardly from a substrate, a second fin protruding upwardly from the substrate, a first gate structure having a first portion that at least partially wraps around an upper portion of the first fin and a second portion that at least partially wraps around an upper portion of the second fin, a second gate structure having a portion that at least partially wraps around the upper portion of the first fin, and a dielectric feature having a first portion between the first and second portions of the first gate structure. In a lengthwise direction of the first fin, the dielectric feature has a second portion extending to a sidewall of the second gate structure.Type: GrantFiled: May 23, 2024Date of Patent: July 1, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pei-Yu Wang, Zhi-Chang Lin, Ching-Wei Tsai, Kuan-Lun Cheng
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Publication number: 20250203955Abstract: A device and method of forming a device are provided. The method includes forming a stack of nanostructure channels over a substrate by forming a source/drain opening. The method also includes forming a sacrificial source/drain in the source/drain opening. The method further includes increasing tensile strain of the stack of nanostructure channels by replacing the sacrificial source/drain with a replacement source/drain having germanium concentration that exceeds that of the sacrificial source/drain.Type: ApplicationFiled: June 4, 2024Publication date: June 19, 2025Inventors: Hsien-Chih HUANG, Guan-Lin CHEN, Chia-Hao YU, Pei-Yu WANG, Chih-Hao WANG
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Publication number: 20250203970Abstract: A method for fabricating a semiconductor device is disclosed. The method involves forming a stack of alternating semiconductor channels and interposers on a substrate, with sacrificial structures between the interposers. Source/drain openings are formed, and strain in the channels is modified. Source/drain structures are formed in the openings, and dielectric layers are deposited. The resulting device features stacked nanostructures with inner spacers of varying heights, enabling improved performance in electronic devices.Type: ApplicationFiled: May 30, 2024Publication date: June 19, 2025Inventors: Guan-Lin CHEN, Chih-Hao WANG, Chia-Hao YU, Pei-Yu WANG, Hsien-Chih HUANG
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Publication number: 20250185306Abstract: Various embodiments of the present disclosure provide a semiconductor device structure including a source/drain feature disposed over a substrate, a plurality of semiconductor layers vertically stacked over the substrate and in contact with the source/drain feature, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, a first dielectric spacer in contact with a first side of a topmost semiconductor layer of the plurality of semiconductor layers, and a second dielectric spacer in contact with a second side of the topmost semiconductor layer of the plurality of semiconductor layers.Type: ApplicationFiled: April 23, 2024Publication date: June 5, 2025Inventors: Chih-Hao WANG, Guan-Lin CHEN, Hsien-Chih HUANG, Chia-Hao YU, Pei-Yu WANG
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Publication number: 20250183159Abstract: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, an epitaxial regrowth layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is over a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is over a backside of the source epitaxial structure and a backside of the drain epitaxial structure. The epitaxial regrowth layer is on the backside of a first one of the source epitaxial structure and the drain epitaxial structure. The backside via extends through the backside dielectric layer and overlaps the epitaxial regrowth layer.Type: ApplicationFiled: January 30, 2025Publication date: June 5, 2025Inventors: Pei-Yu Wang, Yu-Xuan Huang
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Patent number: 12300739Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.Type: GrantFiled: February 26, 2024Date of Patent: May 13, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Min Cao, Pei-Yu Wang, Sai-Hooi Yeong, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 12300720Abstract: A semiconductor device includes a substrate, nanostructures vertically suspended above the substrate, a metal gate structure wrapping each of the nanostructures, an epitaxial feature having a first sidewall in physical contact with end portions of the nanostructures, and an air gap disposed between the epitaxial feature and the metal gate structure. The air gap exposes the first sidewall of the epitaxial feature and the end portions of the nanostructures.Type: GrantFiled: July 28, 2023Date of Patent: May 13, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pei-Yu Wang, Wei Ju Lee
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Patent number: 12300728Abstract: In an embodiment, a device includes: a first nanostructure over a substrate, the first nanostructure including a channel region and a first lightly doped source/drain region, the first lightly doped source/drain region adjacent the channel region; a first epitaxial source/drain region wrapped around four sides of the first lightly doped source/drain region; an interlayer dielectric over the first epitaxial source/drain region; a source/drain contact extending through the interlayer dielectric, the source/drain contact wrapped around four sides of the first epitaxial source/drain region; and a gate stack adjacent the source/drain contact and the first epitaxial source/drain region, the gate stack wrapped around four sides of the channel region.Type: GrantFiled: February 19, 2024Date of Patent: May 13, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sai-Hooi Yeong, Pei-Yu Wang, Chi On Chui
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Publication number: 20250151326Abstract: A method for forming transistors includes forming a stack of alternating first semiconductor layers and second semiconductor layers on a substrate and forming nanostructure channels and interposers by forming a source/drain opening in a first device region of the substrate. The source/drain opening extending through the first and second semiconductor layers. The method includes, after the forming a source/drain opening, increasing tensile strain of the nanostructure channels, and, after the increasing tensile strain, forming a source/drain in the source/drain opening.Type: ApplicationFiled: April 25, 2024Publication date: May 8, 2025Inventors: Guan-Lin CHEN, Chih-Hao WANG, Pei-Yu WANG, Hsien-Chih HUANG, Chia-Hao YU
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Patent number: 12261089Abstract: A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.Type: GrantFiled: January 2, 2024Date of Patent: March 25, 2025Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Tsung-Yu Lin, Pei-Yu Wang, Chung-Wei Hsu
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Patent number: 12249575Abstract: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, an epitaxial regrowth layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is over a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is over a backside of the source epitaxial structure and a backside of the drain epitaxial structure. The epitaxial regrowth layer is on the backside of a first one of the source epitaxial structure and the drain epitaxial structure. The backside via extends through the backside dielectric layer and overlaps the epitaxial regrowth layer.Type: GrantFiled: April 18, 2023Date of Patent: March 11, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pei-Yu Wang, Yu-Xuan Huang
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Publication number: 20250058412Abstract: A laser welding mechanism includes a main body having a space and two securing devices which are respectively attached to two ends of the body. A linkage assembly includes a bearing and a linkage tube. A refraction mirror unit includes two mirrors connected to the linkage tube of the linkage assembly. A laser unit is pivotally connected to a swinging member which is connected to the linkage tube of the linkage assembly. A drive unit including a motor, a driving gear, and a driven gear. A rotation unit is connected to the swinging member of the laser unit. The laser unit rotates relative to the first workpiece and the second workpiece during welding, ensuring a stable rotation at the joining faces of the two workpieces.Type: ApplicationFiled: October 17, 2023Publication date: February 20, 2025Inventors: KUO CHIANG TSENG, NAN KAI WENG, CHIH YU WENG, PEI YU WANG, TZU WEN SUNG, FENG CHI WEI, MAO TE CHUANG
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Patent number: 12211900Abstract: A device includes a first semiconductor strip protruding from a substrate, a second semiconductor strip protruding from the substrate, an isolation material surrounding the first semiconductor strip and the second semiconductor strip, a nanosheet structure over the first semiconductor strip, wherein the nanosheet structure is separated from the first semiconductor strip by a first gate structure including a gate electrode material, wherein the first gate structure partially surrounds the nanosheet structure, and a first semiconductor channel region and a semiconductor second channel region over the second semiconductor strip, wherein the first semiconductor channel region is separated from the second semiconductor channel region by a second gate structure including the gate electrode material, wherein the second gate structure extends on a top surface of the second semiconductor strip.Type: GrantFiled: July 13, 2023Date of Patent: January 28, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pei-Yu Wang, Pei-Hsun Wang
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Patent number: 12202642Abstract: An anti-opening container includes a first box and a second box. The first box includes a first body, a first box section and a first gripping section. The first box section is formed by the extension of the first body. The second box includes a second body, a second box section, a second gripping section, an extension section, and a fastener section. The second box section is formed by the extension of the second body. The fastener section is connected to the extension section via a perforated line. The fastener section is embedded in the first box section. When the first gripping section and the second gripping section are displaced in opposite directions, the perforated line breaks, and the first box section and the fastener section are separated from the second box section together to separate the first box and the second box.Type: GrantFiled: February 22, 2023Date of Patent: January 21, 2025Assignee: SOUTH PLASTIC INDUSTRY CO., LTD.Inventors: Tong-Chang Wang, Pei-Yu Wang
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Publication number: 20250006807Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.Type: ApplicationFiled: September 16, 2024Publication date: January 2, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Chuan Chiu, Huan-Chieh Su, Pei-Yu Wang, Cheng-Chi Chuang, Chun-Yuan Chen, Li-Zhen Yu, Chia-Hao Chang, Yu-Ming Lin, Chih-Hao Wang