Patents by Inventor Pei Yu Wang

Pei Yu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250234595
    Abstract: Inner spacers between a source/drain region of a nanostructure transistor and sacrificial nanostructure layers of the nanostructure transistor are removed prior to formation of a gate structure of the nanostructure transistor. The sacrificial nanostructure layers are removed, and then the inner spacers are removed. The sacrificial nanostructure layers are then replaced with the gate structure of the nanostructure transistor such that the gate structure and the source/drain region are spaced apart by air gaps that result from the removal of the inner spacers. The dielectric constant (or relative permittivity) of the air gaps between the source/drain region and the gate structure is less than the dielectric constant of the material of the inner spacers. The lesser dielectric constant of the air gaps reduces the amount of capacitance between the source/drain region and the gate structure.
    Type: Application
    Filed: May 22, 2024
    Publication date: July 17, 2025
    Inventors: Hsien-Chih HUANG, Guang-Lin CHEN, Pei-Yu WANG, Chia-Hao YU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250226271
    Abstract: A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.
    Type: Application
    Filed: March 25, 2025
    Publication date: July 10, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tsung-Yu LIN, Pei-Yu WANG, Chung-Wei HSU
  • Patent number: 12347690
    Abstract: A semiconductor device includes a first fin protruding upwardly from a substrate, a second fin protruding upwardly from the substrate, a first gate structure having a first portion that at least partially wraps around an upper portion of the first fin and a second portion that at least partially wraps around an upper portion of the second fin, a second gate structure having a portion that at least partially wraps around the upper portion of the first fin, and a dielectric feature having a first portion between the first and second portions of the first gate structure. In a lengthwise direction of the first fin, the dielectric feature has a second portion extending to a sidewall of the second gate structure.
    Type: Grant
    Filed: May 23, 2024
    Date of Patent: July 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Yu Wang, Zhi-Chang Lin, Ching-Wei Tsai, Kuan-Lun Cheng
  • Publication number: 20250203955
    Abstract: A device and method of forming a device are provided. The method includes forming a stack of nanostructure channels over a substrate by forming a source/drain opening. The method also includes forming a sacrificial source/drain in the source/drain opening. The method further includes increasing tensile strain of the stack of nanostructure channels by replacing the sacrificial source/drain with a replacement source/drain having germanium concentration that exceeds that of the sacrificial source/drain.
    Type: Application
    Filed: June 4, 2024
    Publication date: June 19, 2025
    Inventors: Hsien-Chih HUANG, Guan-Lin CHEN, Chia-Hao YU, Pei-Yu WANG, Chih-Hao WANG
  • Publication number: 20250203970
    Abstract: A method for fabricating a semiconductor device is disclosed. The method involves forming a stack of alternating semiconductor channels and interposers on a substrate, with sacrificial structures between the interposers. Source/drain openings are formed, and strain in the channels is modified. Source/drain structures are formed in the openings, and dielectric layers are deposited. The resulting device features stacked nanostructures with inner spacers of varying heights, enabling improved performance in electronic devices.
    Type: Application
    Filed: May 30, 2024
    Publication date: June 19, 2025
    Inventors: Guan-Lin CHEN, Chih-Hao WANG, Chia-Hao YU, Pei-Yu WANG, Hsien-Chih HUANG
  • Publication number: 20250183159
    Abstract: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, an epitaxial regrowth layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is over a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is over a backside of the source epitaxial structure and a backside of the drain epitaxial structure. The epitaxial regrowth layer is on the backside of a first one of the source epitaxial structure and the drain epitaxial structure. The backside via extends through the backside dielectric layer and overlaps the epitaxial regrowth layer.
    Type: Application
    Filed: January 30, 2025
    Publication date: June 5, 2025
    Inventors: Pei-Yu Wang, Yu-Xuan Huang
  • Publication number: 20250151326
    Abstract: A method for forming transistors includes forming a stack of alternating first semiconductor layers and second semiconductor layers on a substrate and forming nanostructure channels and interposers by forming a source/drain opening in a first device region of the substrate. The source/drain opening extending through the first and second semiconductor layers. The method includes, after the forming a source/drain opening, increasing tensile strain of the nanostructure channels, and, after the increasing tensile strain, forming a source/drain in the source/drain opening.
    Type: Application
    Filed: April 25, 2024
    Publication date: May 8, 2025
    Inventors: Guan-Lin CHEN, Chih-Hao WANG, Pei-Yu WANG, Hsien-Chih HUANG, Chia-Hao YU
  • Patent number: 12261089
    Abstract: A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.
    Type: Grant
    Filed: January 2, 2024
    Date of Patent: March 25, 2025
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tsung-Yu Lin, Pei-Yu Wang, Chung-Wei Hsu
  • Patent number: 12249575
    Abstract: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, an epitaxial regrowth layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is over a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is over a backside of the source epitaxial structure and a backside of the drain epitaxial structure. The epitaxial regrowth layer is on the backside of a first one of the source epitaxial structure and the drain epitaxial structure. The backside via extends through the backside dielectric layer and overlaps the epitaxial regrowth layer.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: March 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pei-Yu Wang, Yu-Xuan Huang
  • Publication number: 20250058412
    Abstract: A laser welding mechanism includes a main body having a space and two securing devices which are respectively attached to two ends of the body. A linkage assembly includes a bearing and a linkage tube. A refraction mirror unit includes two mirrors connected to the linkage tube of the linkage assembly. A laser unit is pivotally connected to a swinging member which is connected to the linkage tube of the linkage assembly. A drive unit including a motor, a driving gear, and a driven gear. A rotation unit is connected to the swinging member of the laser unit. The laser unit rotates relative to the first workpiece and the second workpiece during welding, ensuring a stable rotation at the joining faces of the two workpieces.
    Type: Application
    Filed: October 17, 2023
    Publication date: February 20, 2025
    Inventors: KUO CHIANG TSENG, NAN KAI WENG, CHIH YU WENG, PEI YU WANG, TZU WEN SUNG, FENG CHI WEI, MAO TE CHUANG
  • Patent number: 12211900
    Abstract: A device includes a first semiconductor strip protruding from a substrate, a second semiconductor strip protruding from the substrate, an isolation material surrounding the first semiconductor strip and the second semiconductor strip, a nanosheet structure over the first semiconductor strip, wherein the nanosheet structure is separated from the first semiconductor strip by a first gate structure including a gate electrode material, wherein the first gate structure partially surrounds the nanosheet structure, and a first semiconductor channel region and a semiconductor second channel region over the second semiconductor strip, wherein the first semiconductor channel region is separated from the second semiconductor channel region by a second gate structure including the gate electrode material, wherein the second gate structure extends on a top surface of the second semiconductor strip.
    Type: Grant
    Filed: July 13, 2023
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pei-Yu Wang, Pei-Hsun Wang
  • Patent number: 12202642
    Abstract: An anti-opening container includes a first box and a second box. The first box includes a first body, a first box section and a first gripping section. The first box section is formed by the extension of the first body. The second box includes a second body, a second box section, a second gripping section, an extension section, and a fastener section. The second box section is formed by the extension of the second body. The fastener section is connected to the extension section via a perforated line. The fastener section is embedded in the first box section. When the first gripping section and the second gripping section are displaced in opposite directions, the perforated line breaks, and the first box section and the fastener section are separated from the second box section together to separate the first box and the second box.
    Type: Grant
    Filed: February 22, 2023
    Date of Patent: January 21, 2025
    Assignee: SOUTH PLASTIC INDUSTRY CO., LTD.
    Inventors: Tong-Chang Wang, Pei-Yu Wang
  • Publication number: 20250006807
    Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.
    Type: Application
    Filed: September 16, 2024
    Publication date: January 2, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chuan Chiu, Huan-Chieh Su, Pei-Yu Wang, Cheng-Chi Chuang, Chun-Yuan Chen, Li-Zhen Yu, Chia-Hao Chang, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20240395861
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes channel layers, a mask structure, a gate structure and a source/drain pattern. The channel layers are stacked vertically apart along a first direction over a substrate. The mask structure is disposed over and apart from the channel layers along the first direction. The gate structure laterally extends along a second direction perpendicular to the first direction disposed, wherein the gate structure wraps around the channel layers and laterally surround the mask structure. The source/drain pattern is in contact with the channel layers.
    Type: Application
    Filed: May 24, 2023
    Publication date: November 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Yu Wang, Wang-Chun Huang, Cheng-Ting Chung, Yi-Bo Liao
  • Publication number: 20240387732
    Abstract: Embodiments of the present disclosure provide a method for forming backside metal contacts with reduced Cgd and increased speed. Particularly, source/drain features on the drain side, or source/drain features without backside metal contact, are recessed from the backside to the level of the inner spacer to reduce Cgd. Some embodiments of the present disclosure use a sacrificial liner to protect backside alignment feature during backside processing, thus, preventing shape erosion of metal conducts and improving device performance.
    Type: Application
    Filed: July 28, 2024
    Publication date: November 21, 2024
    Inventors: CHUN-YUAN CHEN, HUAN-CHIEH SU, PEI-YU WANG, CHIH-HAO WANG
  • Patent number: 12148837
    Abstract: In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Bo Liao, Yu-Xuan Huang, Pei-Yu Wang, Cheng-Ting Chung, Ching-Wei Tsai, Hou-Yu Chen
  • Patent number: 12148805
    Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Chuan Chiu, Huan-Chieh Su, Pei-Yu Wang, Cheng-Chi Chuang, Chun-Yuan Chen, Li-Zhen Yu, Chia-Hao Chang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 12148830
    Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Chieh Yang, Wei Ju Lee, Li-Yang Chuang, Pei-Yu Wang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Publication number: 20240379807
    Abstract: A method according to the present disclosure includes providing a workpiece. The workpiece includes a fin-shaped structure including a channel region and a source/drain region, a metal gate structure disposed over the channel region, a dummy source/drain feature disposed over the source/drain region, and a dielectric structure disposed over the dummy source/drain feature. The method further includes forming a trench through the dielectric structure and the dummy source/drain feature to expose a sidewall of the channel region, forming an epitaxial layer over the sidewall of the channel region, and forming a metal feature over a sidewall of the epitaxial layer and in the trench.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventor: Pei-Yu Wang
  • Publication number: 20240379849
    Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Kai-Chieh Yang, Wei Ju Lee, Li-Yang Chuang, Pei-Yu Wang, Ching-Wei Tsai, Kuan-Lun Cheng