Patents by Inventor Peng Fu
Peng Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8384159Abstract: A semiconductor device is disclosed that includes: a substrate; a first dielectric layer formed over the substrate and formed of a first high-k material, the first high-k material selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; a second dielectric layer formed over the first dielectric layer and formed of a second high-k material, the second high-k material being different than the first high-k material and selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; and a metal gate formed over the second dielectric layer. The first dielectric layer includes ions selected from the group consisting of N, O, and Si.Type: GrantFiled: April 20, 2009Date of Patent: February 26, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fong-Yu Yen, Cheng-Lung Hung, Peng-Fu Hsu, Vencent S. Chang, Yong-Tian Hou, Jin Ying, Hun-Jan Tao
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Patent number: 8324090Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first capping layer and a second capping layer over the high-k dielectric layer, the first capping layer overlying the first region and the second capping layer overlying the second region, forming a layer containing silicon (Si) over the first and second capping layers, forming a metal layer over the layer containing Si, and forming a first gate stack over the first region and a second gate stack over the second active region.Type: GrantFiled: December 18, 2008Date of Patent: December 4, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yuri Masuoka, Peng-Fu Hsu, Huan-Tsung Huang, Kuo-Tai Huang, Yong-Tian Hou, Carlos H. Diaz
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Publication number: 20120193802Abstract: A semiconductor package is disclosed including a substrate, a solder mask layer, one or more semiconductor die mounted to the solder mask layer and electrically coupled to the substrate, and a glob top cover over the semiconductor die. The solder mask further includes a dam protruding above surrounding areas of the solder mask layer and a cavity recessed into the solder mask layer for limiting flow of the glob top cover when the glob top material is applied.Type: ApplicationFiled: February 1, 2011Publication date: August 2, 2012Inventors: Chin-Tien Chiu, Chih-Chin Liao, Peng Fu
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Publication number: 20120146247Abstract: A memory device is disclosed including at least one surface pre-treated to roughen the surface for better adhesion of a curable fluid such as glue or ink on the surface. The surface of the memory device may be pre-treated by scoring lines in the surface with a laser or by forming discrete deformations with a particle blaster. The surface may also be roughened by providing a roughened pattern on a mold plate during an encapsulation process. In further examples, the surface may be chemically pre-treated to roughen the surface and/or increase the adhesion energy of the surface.Type: ApplicationFiled: June 8, 2011Publication date: June 14, 2012Inventors: Itzhak Pomerantz, Shiv Kumar, Robert Miller, Chin-Tien Chiu, Peng Fu, Cheeman Yu, Hem Takiar, Chih Chiang Tung, Kaiyou Qian, Rahav Yairi
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Publication number: 20120086085Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer in the first region, forming a first metal layer over capping layer in the first region and over the high-k dielectric in the second region, thereafter, forming a first gate stack in the first region and a second gate stack in the second region, protecting the first metal layer in the first gate stack while performing a treatment process on the first metal layer in the second gate stack, and forming a second metal layer over the first metal layer in the first gate stack and over the treated first metal layer in the second gate stack.Type: ApplicationFiled: December 19, 2011Publication date: April 12, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Peng-Fu Hsu, Kang-Cheng Lin, Kuo-Tai Huang
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Publication number: 20120081860Abstract: A memory device is disclosed including at least one surface pre-treated to roughen the surface for better adhesion of ink on the surface. The surface of the memory device may be pre-treated by scoring lines in the surface with a laser or by forming discrete deformations with a particle blaster. The surface may also be roughened by providing a roughened pattern on a mold plate during an encapsulation process. In further examples, the surface may be chemically pre-treated to roughen the surface and/or increase the adhesion energy of the surface.Type: ApplicationFiled: October 4, 2010Publication date: April 5, 2012Inventors: Itzhak Pomerantz, Shiv Kumar, Robert Miller, Chin-Tien Chiu, Peng Fu, Cheeman Yu, Hem Takiar, Chih Chiang Tung, Kaiyou Qian
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Patent number: 8105931Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer in the first region, forming a first metal layer over capping layer in the first region and over the high-k dielectric in the second region, thereafter, forming a first gate stack in the first region and a second gate stack in the second region, protecting the first metal layer in the first gate stack while performing a treatment process on the first metal layer in the second gate stack, and forming a second metal layer over the first metal layer in the first gate stack and over the treated first metal layer in the second gate stack.Type: GrantFiled: April 16, 2009Date of Patent: January 31, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Peng-Fu Hsu, Kang-Cheng Lin, Kuo-Tai Huang
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Patent number: 7989321Abstract: A method is provided that allows for maintaining a desired equivalent oxide thickness (EOT) by reducing the thickness of an interfacial layer in a gate structure. An interfacial layer is formed on a substrate, a gate dielectric layer such as, a high-k gate dielectric, is formed on the interfacial layer. A gettering layer is formed on the substrate overlying the interfacial layer. The gettering layer may function to getter oxygen from the interfacial layer such that the interfacial layer thickness is decreased and/or restricted from growth.Type: GrantFiled: October 23, 2008Date of Patent: August 2, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hao Chen, Yong-Tian Hou, Peng-Fu Hsu, Kuo-Tai Huang, Donald Y. Chao, Cheng-Lung Hung
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Patent number: 7947591Abstract: Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed on the second doped region. A sealing layer is disposed on sidewalls of the first gate stack and the second gate stack. The first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer. The second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer.Type: GrantFiled: April 9, 2008Date of Patent: May 24, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Peng-Fu Hsu, Fong-Yu Yen, Yi-Shien Mor, Huan-Just Lin, Ying Jin, Hun-Jan Tao
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Patent number: 7939396Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate, performing a hydrogen annealing to the semiconductor substrate, forming a base oxide layer after the step of hydrogen annealing, and forming a high-k dielectric layer on the base oxide layer.Type: GrantFiled: June 9, 2006Date of Patent: May 10, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Peng-Fu Hsu, Jin Ying, Hun-Jan Tao
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Patent number: 7875547Abstract: Methods and structures for forming a contact hole structure are disclosed. These methods first form a substantially silicon-free material layer over a substrate. A material layer is formed over the substantially silicon-free material layer. A contact hole is formed within the substantially silicon-free material layer and the material layer without substantially damaging the substrate. In addition, a conductive layer is formed in the contact hole so as to form a contact structure.Type: GrantFiled: January 12, 2005Date of Patent: January 25, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ju-Wang Hsu, Jyu-Horng Shieh, Yi-Nien Su, Peng-Fu Hsu, Hun-Jan Tao
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Publication number: 20110001194Abstract: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.Type: ApplicationFiled: September 16, 2010Publication date: January 6, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yong-Tian Hou, Peng-Fu Hsu, Jin Ying, Kang-Cheng Lin, K. T. Huang, Tze-Liang Lee
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Patent number: 7812414Abstract: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.Type: GrantFiled: January 23, 2007Date of Patent: October 12, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yong-Tian Hou, Peng-Fu Hsu, Jin Ying, Kang-Cheng Lin, Kuo-Tai Huang, Tze-Liang Lee
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Patent number: 7732878Abstract: A semiconductor structure includes a substrate, a gate stack on the substrate, a source/drain region adjacent the gate stack, a source/drain silicide region on the source/drain region, a protection layer on the source/drain silicide region, wherein a region over the gate stack is substantially free from the protection layer, and a contact etch stop layer (CESL) having a stress over the protection layer and extending over the gate stack.Type: GrantFiled: October 18, 2006Date of Patent: June 8, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Liang-Gi Yao, Shiang-Bau Wang, Huan-Just Lin, Peng-Fu Hsu, Jin Ying, Hun-Jan Tao
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Publication number: 20100052067Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer in the first region, forming a first metal layer over capping layer in the first region and over the high-k dielectric in the second region, thereafter, forming a first gate stack in the first region and a second gate stack in the second region, protecting the first metal layer in the first gate stack while performing a treatment process on the first metal layer in the second gate stack, and forming a second metal layer over the first metal layer in the first gate stack and over the treated first metal layer in the second gate stack.Type: ApplicationFiled: April 16, 2009Publication date: March 4, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Peng-Fu Hsu, Kang-Cheng Lin, Kuo-Tai Huang
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Publication number: 20100052063Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first capping layer and a second capping layer over the high-k dielectric layer, the first capping layer overlying the first region and the second capping layer overlying the second region, forming a layer containing silicon (Si) over the first and second capping layers, forming a metal layer over the layer containing Si, and forming a first gate stack over the first region and a second gate stack over the second active region.Type: ApplicationFiled: December 18, 2008Publication date: March 4, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yuri Masuoka, Peng-Fu Hsu, Huan-Tsung Huang, Kuo-Tai Huang, Carlos H. Diaz, Yong-Tian Hou
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Publication number: 20100052077Abstract: A high-k metal gate structure including a buffer layer and method of fabrication of such, is provided. The buffer layer may interpose an interface oxide layer and a high-k gate dielectric layer. In one embodiment, the buffer layer includes aluminum oxide. The buffer layer and the high-k gate dielectric layer may be formed in-situ using an atomic layer deposition (ALD) process.Type: ApplicationFiled: April 13, 2009Publication date: March 4, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Peng-Fu Hsu, Hsin-Chun Ko, Kang-Cheng Lin, Kuo-Tai Huang
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Publication number: 20100048010Abstract: A method is provided that allows for maintaining a desired equivalent oxide thickness (EOT) by reducing the thickness of an interfacial layer in a gate structure. An interfacial layer is formed on a substrate, a gate dielectric layer such as, a high-k gate dielectric, is formed on the interfacial layer. A gettering layer is formed on the substrate overlying the interfacial layer. The gettering layer may function to getter oxygen from the interfacial layer such that the interfacial layer thickness is decreased and/or restricted from growth.Type: ApplicationFiled: October 23, 2008Publication date: February 25, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Hao Chen, Yong-Tian Hou, Peng-Fu Hsu, Kuo-Tai Huang, Donald Y. Chao, Cheng-Lung Hung
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Patent number: 7663185Abstract: A fin-FET device and a method for fabrication thereof both employ a bulk semiconductor substrate. A fin and an adjoining trough are formed within the bulk semiconductor substrate. The trough is partially backfilled with a deposited dielectric layer to form an exposed fin region and an unexposed fin region. A gate dielectric layer is formed upon the exposed fin region and a gate electrode is formed upon the gate dielectric layer. By employing a bulk semiconductor substrate the fin-FET device is fabricated cost effectively.Type: GrantFiled: May 27, 2006Date of Patent: February 16, 2010Assignee: Taiwan Semiconductor Manufacturing Co, LtdInventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Jhi-Cherng Lu, Chuan-Ping Hou, Peng-Fu Hsu, Hung-Wei Chen, Di-Hong Lee
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Publication number: 20090315125Abstract: A semiconductor device is disclosed that includes: a substrate; a first dielectric layer formed over the substrate and formed of a first high-k material, the first high-k material selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; a second dielectric layer formed over the first dielectric layer and formed of a second high-k material, the second high-k material being different than the first high-k material and selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; and a metal gate formed over the second dielectric layer. The first dielectric layer includes ions selected from the group consisting of N, O, and Si.Type: ApplicationFiled: April 20, 2009Publication date: December 24, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fong-Yu YEN, Cheng-Lung HUNG, Peng-Fu HSU, Vencent S. CHANG, Yong-Tian HOU, Jin YING, Hun-Jan TAO