Abstract: A package structure is provided. The package structure includes a leadframe including a first portion and a second portion. The first portion includes a first base part and a plurality of first extended parts connected to the first base part. The second portion includes a second base part and a plurality of second extended parts connected to the second base part. The first extended parts and the second extended parts are arranged in such a way that they alternate with each other. In the package structure, a chip is disposed on a part of the first extended parts of the first portion and the second extended parts of the second portion of the leadframe. The package structure further includes a plurality of protrusions, opposite to the chip, disposed on the first extended parts and the second extended parts.

Abstract: A semiconductor device includes a substrate and a chip. The substrate has a first conduction layer, a second conduction layer, and an isolation layer disposed between the first conduction layer and the second conduction layer. The first conductive layer has a first portion and a second portion spaced apart from the first portion, and each of the first portion and the second portion includes a main part and a plurality of extension parts extending from the main part. The chip is disposed on the extension parts of the first portion and the second portion of the first conductive layer.

Abstract: A package structure is provided. The package structure includes a leadframe including a first portion and a second portion. The first portion includes a first base part and a plurality of first extended parts connected to the first base part. The second portion includes a second base part and a plurality of second extended parts connected to the second base part. The first extended parts and the second extended parts are arranged in such a way that they alternate with each other. In the package structure, a chip is disposed on a part of the first extended parts of the first portion and the second extended parts of the second portion of the leadframe.

Abstract: A package structure is provided. The package structure includes a leadframe including a first portion and a second portion. The first portion includes a first base part and a plurality of first extended parts connected to the first base part. The second portion includes a second base part and a plurality of second extended parts connected to the second base part. The first extended parts and the second extended parts are arranged in such a way that they alternate with each other. In the package structure, a chip is disposed on a part of the first extended parts of the first portion and the second extended parts of the second portion of the leadframe. The package structure further includes a plurality of protrusions, opposite to the chip, disposed on the first extended parts and the second extended parts.

Abstract: A packaging device including a first semiconductor device, a thermal dissipating component, an encapsulation layer, a via, and a pad. The first semiconductor device includes a substrate, an active region, and an electrode. The active region is disposed between the substrate and the electrode. The substrate has a first surface opposite to the active region, and the electrode has a second surface opposite to the active region. The thermal dissipating component is disposed on the first surface of the substrate. The encapsulation layer encloses the second surface of the electrode and a part of the thermal dissipating component, such that another part of the thermal dissipating component is exposed by the encapsulation layer. The pad is disposed on the encapsulation layer. The via is disposed in the encapsulation layer and connects the pad to the electrode.

Abstract: A package structure is provided. The package structure includes a leadframe including a plurality of connection portions; a device including a substrate, an active layer disposed on the substrate and a plurality of electrodes disposed on the active layer, wherein the electrodes of the device are connected to the connection portions of the leadframe; a conductive unit having a first side and a second side, wherein the first side of the conductive unit connects to the substrate of the device and the conductive unit connects to at least one of the connection portions of the leadframe; and an encapsulation material covering the device and the leadframe, wherein the second side of the conductive unit is exposed from the encapsulation material.

Abstract: A packaging device including a first semiconductor device, a thermal dissipating component, an encapsulation layer, a via, and a pad. The first semiconductor device includes a substrate, an active region, and an electrode. The active region is disposed between the substrate and the electrode. The substrate has a first surface opposite to the active region, and the electrode has a second surface opposite to the active region. The thermal dissipating component is disposed on the first surface of the substrate. The encapsulation layer encloses the second surface of the electrode and a part of the thermal dissipating component, such that another part of the thermal dissipating component is exposed by the encapsulation layer. The pad is disposed on the encapsulation layer. The via is disposed in the encapsulation layer and connects the pad to the electrode.

Abstract: A package structure includes a first conduction layer, a second conduction layer, and an isolation layer. The first conduction layer includes a plurality of first portions, and the second conduction layer includes a plurality of portions. The isolation layer is disposed between the first conduction layer and the second conduction layer, and the isolation layer is composed of one of nitride and oxide mixed with at least one of epoxy and polymer.

Abstract: A semiconductor device includes a substrate and a chip. The substrate has a first conduction layer, a second conduction layer, and an isolation layer disposed between the first conduction layer and the second conduction layer. The first conductive layer has a first portion and a second portion spaced apart from the first portion, and each of the first portion and the second portion includes a main part and a plurality of extension parts extending from the main part. The chip is disposed on the extension parts of the first portion and the second portion of the first conductive layer.

Abstract: A packaging device including a first semiconductor device, a thermal dissipating component, an encapsulation layer, a via, and a pad. The first semiconductor device includes a substrate, an active region, and an electrode. The active region is disposed between the substrate and the electrode. The substrate has a first surface opposite to the active region, and the electrode has a second surface opposite to the active region. The thermal dissipating component is disposed on the first surface of the substrate. The encapsulation layer encloses the second surface of the electrode and a part of the thermal dissipating component, such that another part of the thermal dissipating component is exposed by the encapsulation layer. The pad is disposed on the encapsulation layer. The via is disposed in the encapsulation layer and connects the pad to the electrode.

Abstract: A method of forming an interconnection structure is disclosed, including providing a substrate having a first side and a second side opposite to the first side, forming a via hole through the substrate, wherein the via hole has a first opening in the first side and a second opening in the second side, forming a first pad covering the first opening, and forming a via structure in the via hole subsequent to forming the first pad, wherein the via structure includes a conductive material and is adjoined to the first pad.

Abstract: A packaging structure is provided, including a substrate, a first chip, a second chip, and a conductive unit. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip by the conductive unit.

Abstract: A package structure is provided. The package structure includes a leadframe including a plurality of connection portions; a device including a substrate, an active layer disposed on the substrate and a plurality of electrodes disposed on the active layer, wherein the electrodes of the device are connected to the connection portions of the leadframe; a conductive unit having a first side and a second side, wherein the first side of the conductive unit connects to the substrate of the device and the conductive unit connects to at least one of the connection portions of the leadframe; and an encapsulation material covering the device and the leadframe, wherein the second side of the conductive unit is exposed from the encapsulation material.

Abstract: A power module package is provided, including a substrate, a first chip, and a second chip. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip.

Abstract: A power module package is provided, including a substrate, a first chip, and a second chip. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip.

Abstract: A package structure includes an encapsulant, an active component, a first lead frame segment, and a second lead frame segment. The active component is encapsulated within the encapsulant and includes first and second electrodes. The first and second electrodes are respectively disposed on and electrically connected to the first and second lead frame segments. The first and second lead frame segments respectively have first and second exposed surfaces. The first exposed surface and the first electrode are respectively located on opposite sides of the first lead frame segment. The second exposed surface and the second electrode are respectively located on opposite sides of the second lead frame segment. The first and second exposed surfaces are exposed outside the encapsulant. A minimal distance from the first electrode to the second electrode is less than a minimal distance from the first exposed surface to the second exposed surface.

Abstract: A power module package is provided, including a substrate, a first chip, and a second chip. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip.

Abstract: A power module package is provided, including a substrate, a first chip, and a second chip. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip.

Abstract: A packaging structure is provided, including a substrate, a first chip, a second chip, and a conductive unit. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip by the conductive unit.

Abstract: A packaging structure includes a lead frame, a chip, and a packaging material. The lead frame has a pair of opposed first surface and second surface, and has a first recessed region located on the second surface. The chip has a pair of opposed first surface and second surface. The first surface of the chip is fixed on the first recessed region. The packaging material surrounds the lead frame and the chip. The second surface of the chip is exposed from the packaging material, and the first surface of the lead frame is exposed from the packaging material.