POWER MODULE PACKAGE HAVING PATTERNED INSULATION METAL SUBSTRATE
A power module package is provided, including a substrate, a first chip, and a second chip. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip.
The present application relates to a semiconductor package, and in particular to a power module package having a patterned insulation metal substrate (PIMS).
Description of the Related ArtPower module packages have been widely applied in automobiles, industrial equipment, and household electrical appliances. In general, in power module packages, one or more semiconductor power chips are mounted on a metal carrier and encapsulated with an epoxy molding compound (EMC) to protect internal parts.
However, owing to the aforementioned structural feature of the substrate (the metal carrier 10, the insulation layer 11, and the conductive layer 12 are stacked on each other), the traditional power module package 1 usually has a poor ability to dissipate heat. Consequently, the reliability of the traditional power module package 1 is adversely affected.
BRIEF SUMMARY OF THE INVENTIONIn view of the aforementioned problems, an embodiment of the invention provides a substrate (a patterned insulation metal substrate (PIMS)), comprising a metal carrier, a patterned insulation layer, and a patterned conductive layer. The patterned insulation layer is disposed on the metal carrier and partially covers the metal carrier. The patterned conductive layer is disposed on the patterned insulation layer.
Another embodiment of the invention provides a power module package, comprising a substrate (a patterned insulation metal substrate (PIMS)), a first chip, and a second chip. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and is electrically connected to the first chip.
Another embodiment of the invention provides a method of manufacturing a patterned insulation metal substrate, comprising: providing a substrate including an insulation layer and a patterned conductive layer covering a top surface of the insulation layer; forming an adhesive side on a bottom surface of the insulation layer; forming an opening through the insulation layer; and laminating a patterned metal carrier to the adhesive side of the insulation layer.
Another embodiment of the invention provides a method of manufacturing a patterned insulation metal substrate, comprising: providing a substrate including an insulation layer and a patterned conductive layer covering a top surface of the insulation layer; forming an adhesive side on a bottom surface of the insulation layer; forming an opening through the insulation layer; laminating a metal carrier to the adhesive side of the insulation layer; and patterning the metal carrier.
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
In order to illustrate the purposes, features, and advantages of the invention, the preferred embodiments and drawings of the invention are shown in detail as follows.
In the following detailed description, the orientations of “on”, “above”, “under”, and “below” are used for representing the relationship between the relative positions of each element as illustrated in the drawings, and are not meant to limit the invention.
In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Various features may be arbitrarily drawn in different scales for the sake of simplicity and clarity. Furthermore, some elements not shown or described in the embodiments have the forms known by persons skilled in the field of the invention.
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In this embodiment, the first semiconductor power chip 30 such as a High-Voltage (HV) switch is a lateral semiconductor component, and the second semiconductor power chip 40 such as a Low-Voltage (LV) switch is a vertical semiconductor component.
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Furthermore, in this embodiment, the first semiconductor power chip 30 includes a plurality of HV transistors connected in parallel (not shown in the drawings), wherein each of the HV transistors, such as a lateral type Depletion mode (D-mode) transistor has a first source electrode electrically connected to the first source pad 30S, a first drain electrode electrically connected to the first drain pad 30D, and a first gate electrode electrically connected to the first gate pad 30G. Moreover, each of the HV transistors in the first semiconductor power chip 30 is a nitride-based transistor, such as a High Electron Mobility Transistor (HEMT) comprising Gallium Nitride (GaN). In addition, in this embodiment, the second semiconductor power chip 40 includes a plurality of LV transistors connected in parallel (not shown in the drawings), wherein each of the LV transistors, such as a vertical type Enhancement mode (E-mode) transistor has a second source electrode electrically connected to the second source pad 40S, a second drain electrode electrically connected to the second drain pad, and a second gate electrode electrically connected to the second gate pad 40G. Moreover, each of the LV transistors is a silicon-based transistor.
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With the aforementioned structural features, a cascade switch circuit including the first semiconductor power chip 30, the second semiconductor power chip 40, and the two passive components 50 can be achieved. Compared to a single switch circuit, the cascade switch circuit is better able to supply higher voltage and switch faster.
It should be noted that the power module package 2 described above can be applied to a power related product, such as a transformer or a power supply. Moreover, with the design of the patterned insulation metal substrate (PIMS) 20, the power module package 2 can have a better heat dissipation ability and improved reliability, compared with the traditional power module package 1 (
In the aforementioned embodiment, although the first semiconductor power chip 30 is a lateral semiconductor component, the invention is not limited thereto. In some embodiments, the first semiconductor power chip 30 may also be a vertical semiconductor component if the bottom surface of the metal carrier 22 is covered by an insulation layer. In some embodiments, the first and second semiconductor power chips 30 and 40 may also be other active components or drivers, rather than an HV switch and an LV switch.
Next, some power module packages with different structures in accordance with various embodiments of the invention are illustrated below.
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Furthermore, although the patterned insulation layer 24 surrounds the first semiconductor power chip 30 in this embodiment (
Next, a method of manufacturing the aforementioned patterned insulation metal substrate 20 (
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It should also be realized that, in some embodiments, after the opening 103 through the insulation layer 100 is formed (
As mentioned above, the invention provides a power module package having a patterned insulation metal substrate (PIMS). Since the patterned insulation layer in the PIMS will not block the heat generated from the semiconductor power chips mounted on the PIMS, the power module package can have a better heat dissipation ability and improved reliability.
While the invention has been described by way of example and in terms of the preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims
1. A substrate, comprising:
- a metal carrier;
- a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier; and
- a patterned conductive layer disposed on the patterned insulation layer;
- wherein the metal carrier includes a cavity, a recess or a slot not extended through the metal carrier and not covered by the patterned insulation layer.
2-3. (canceled)
4. The substrate as claimed in claim 1, wherein the metal carrier is a lead frame comprising copper.
5. A power module package, comprising:
- a substrate including a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer;
- a first chip disposed on the metal carrier that includes a cavity, a recess or a slot which is not covered by the patterned insulation layer; and
- a second chip disposed on the patterned conductive layer and electrically connected to the first chip.
6. The power module package as claimed in claim 5, wherein the first chip is disposed in the cavity, the recess or the slot.
7. The power module package as claimed in claim 5, where the patterned insulation layer includes an opening, and the first chip is disposed therein.
8. The power module package as claimed in claim 5, wherein the patterned insulation layer includes a first patterned insulation portion covered by a part of the patterned conductive layer and a second patterned insulation portion, and the second chip is disposed on the part of the patterned conductive layer.
9. The power module package as claimed in claim 5, wherein the patterned insulation layer includes a first patterned insulation portion covered by a part of the patterned conductive layer and a second patterned insulation portion covered by another part of the patterned conductive layer, and the first chip is electrically connected to the another part of the patterned conductive layer.
10. The power module package as claimed in claim 5, wherein the first chip is directly connected to the metal carrier.
11. The power module package as claimed in claim 5, wherein the metal carrier is a lead frame comprising copper.
12. The power module package as claimed in claim 5, wherein the first chip is a lateral semiconductor component.
13. The power module package as claimed in claim 5, wherein the second chip is a vertical semiconductor component.
14. The power module package as claimed in claim 5, wherein the first chip has an active side with electrodes thereon and a bottom side opposite to the active side, and the first chip is disposed on the metal carrier via the bottom side.
15. The substrate as claimed in claim 1, wherein the cavity, recess or slot is formed on the metal carrier and/or that the metal carrier includes first, second and third sections formed with a gap therebetween and connected by wire with each other and the cavity, recess or slot is formed in the second section of the metal carrier.
16. The power module package as claimed in claim 5, wherein the cavity, recess or slot is formed on the metal carrier and/or that the metal carrier includes first, second and third sections formed with a gap therebetween and connected by wire with each other and the cavity, recess or slot is formed in the second section of the metal carrier.
Type: Application
Filed: Apr 29, 2016
Publication Date: Nov 2, 2017
Patent Grant number: 9865531
Inventors: Hsin-Chang TSAI (Taoyuan City), Chia-Yen LEE (Taoyuan City), Peng-Hsin LEE (Taoyuan City)
Application Number: 15/142,588