Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a main feature; performing an optical proximity correction (OPC) process to the design layout; and thereafter, performing a jog reduction process to the design layout such that jog features of the design layout are reduced.

Abstract: A method of making a mask includes receiving an IC design layout from a designer, applying an logic operation (LOP) correction, performing an OPC correction, fracturing the modified data into a plurality of main features in an electron beam format, and sending the electron beam format data to a mask writer for a mask fabrication. An XOR operation is implemented into the method to check and verify if a pattern is lost during OPC modification and/or data fracture. A BACKBONE XOR operation is also implemented into the method for a plurality of main features with a critical dimension (CD) size smaller than the max OPC correction to check and verify if a small pattern feature is lost during OPC modification and/or data fracture for 45 nm and beyond semiconductor technologies.

Abstract: An adaptive query execution plan enhancement is provided by: selecting a sample of literal sets from an execution history of a query statement; determining a plurality of access paths by applying each literal set in the sample to the query statement; for each given access path of the plurality of access paths, determining a total execution cost by applying each literal set in the sample to the given access path; and selecting a preferred access path from the plurality of access paths based on the total execution costs for each given access path. A plurality of preferred access paths for a plurality of query statements in an application workload is collected and may be presented as a query execution plan enhancement recommendation to users.

Abstract: A method of making a mask includes receiving an IC design layout from a designer, applying an logic operation (LOP) correction, performing an OPC correction, fracturing the modified data into a plurality of main features in an electron beam format, and sending the electron beam format data to a mask writer for a mask fabrication. An XOR operation is implemented into the method to check and verify if a pattern is lost during OPC modification and/or data fracture. A BACKBONE XOR operation is also implemented into the method for a plurality of main features with a critical dimension (CD) size smaller than the max OPC correction to check and verify if a small pattern feature is lost during OPC modification and/or data fracture for 45 nm and beyond semiconductor technologies.

Abstract: The present invention discloses a system and method for CSCF entity disaster tolerance and load balancing the system comprises P-CSCF entities, I-CSCF entities and S-CSCF entities, and further comprises a DNS Server. The present invention uses a DNS UPDATE message to report the load equivalent weight of the CSCF entity at regular time, so that the DNS Server can use the load equivalent weight when executing the load balancing strategy. It makes the disaster tolerance and load balancing in the IMS network be much easier to use and extend, thus reducing the load of the IMS network.

Abstract: The present disclosure provides for methods of reducing cycle time in data preparation. In one embodiment, a method includes receiving an initial integrated circuit (IC) design layout and an optical proximity correction (OPC)-processed initial IC design layout, and receiving a revised IC design layout. The method further includes comparing the revised IC design layout to the initial IC design layout to identify a difference region of the revised IC design layout from the initial IC design layout, performing an OPC on the difference region of the revised IC design layout, and merging the OPC-processed difference region of the revised IC design layout with the OPC-processed initial IC design layout.

Abstract: The present disclosure provides for methods of reducing cycle time in data preparation. In one embodiment, a method includes receiving an initial integrated circuit (IC) design layout and an optical proximity correction (OPC)-processed initial IC design layout, and receiving a revised IC design layout. The method further includes comparing the revised IC design layout to the initial IC design layout to identify a difference region of the revised IC design layout from the initial IC design layout, performing an OPC on the difference region of the revised IC design layout, and merging the OPC-processed difference region of the revised IC design layout with the OPC-processed initial IC design layout.

Abstract: The present invention discloses an LED structure, wherein an N-type current spreading layer is interposed between N-type semiconductor layers to uniformly distribute current flowing through the N-type semiconductor layer. The N-type current spreading layer includes at least three sub-layers stacked in a sequence of from a lower band gap to a higher band gap, wherein the sub-layer having the lower band gap is near the substrate, and the sub-layer having the higher band gap is near the light emitting layer. Each sub-layer of the N-type current spreading layer is expressed by a general formula InxAlyGa(1-x-y)N, wherein 0?x?1, 0?y?1, and 0?x+y?1.

Abstract: The present invention discloses a system and method for CSCF entity disaster tolerance and load balancing the system comprises P-CSCF entities, I-CSCF entities and S-CSCF entities, and further comprises a DNS Server. The present invention uses a DNS UPDATE message to report the load equivalent weight of the CSCF entity at regular time, so that the DNS Server can use the load equivalent weight when executing the load balancing strategy. It makes the disaster tolerance and load balancing in the IMS network be much easier to use and extend, thus reducing the load of the IMS network.

Abstract: The present invention discloses an LED structure, wherein an N-type current spreading layer is interposed between N-type semiconductor layers to uniformly distribute current flowing through the N-type semiconductor layer. The N-type current spreading layer includes at least three sub-layers stacked in a sequence of from a lower band gap to a higher band gap, wherein the sub-layer having the lower band gap is near the substrate, and the sub-layer having the higher band gap is near the light emitting layer. Each sub-layer of the N-type current spreading layer is expressed by a general formula InxAlyGa(1-x-y)N, wherein 0?x?1, 0?y?1, and 0?x+y?1.

Abstract: The present disclosure provides for many different embodiments. A mask fabrication method and system is provided. The method and system identify critical areas of an integrated circuit (IC) design layout that has undergone optical proximity correction. The critical areas are areas of the OPCed IC design layout that are at risk for hot spots. A lithography process check is then performed on the critical areas of the OPCed IC design layout.

Abstract: A method, computer-readable medium, and system for performing data preparation are provided. An integrated circuit design is received, and a plurality of pre-optical proximity correction processes are invoked such that the plurality of pre-optical proximity correction processes are performed in parallel. An optical proximity correction process is invoked in response to a determination that each of the plurality of pre-optical proximity correction processes have completed. A post-optical proximity correction process is invoked in response to a determination that the optical proximity correction process has completed.

Abstract: A method, computer-readable medium, and system for performing data preparation are provided. An integrated circuit design is received, and a plurality of pre-optical proximity correction processes are invoked such that the plurality of pre-optical proximity correction processes are performed in parallel. An optical proximity correction process is invoked in response to a determination that each of the plurality of pre-optical proximity correction processes have completed.

Abstract: The present invention provides a method and an apparatus for aggregating database runtime information and analyzing application performance. According to one aspect of the present invention, there is provided a method for aggregating database runtime information, comprising: aggregating said database runtime information based on queries; and aggregating, based on objects, said database runtime information that is aggregated based on queries.

Abstract: The application relates to a tool and a method for customizing hint. According to the invention, provided is at least one hint service adapter configured to collect relevant information of different database platforms, validate customized hint on real database platforms and provide feedback, and deploy the customized hint on database platform. Also provided is hint defining means configured to customize hint independently of database platforms, and providing customized hint to the at least one hint service adapter.