Abstract: Methods for minimizing plasma-induced sidewall damage during low k etch processes are disclosed. The methods etch the low k layers using the plasma activated vapor of an organofluorine compound having a formula selected from the group consisting of N?C—R; (N?C—)—(R)—(—C?N); Rx[—C?N(Rz)]y; and R(3-a)—N—Ha, wherein a=1-2, x=1-2, y=1-2, z=0-1, x+z=1-3, and each R independently has the formula HaFbCc with a=0-11, b=0-11, and c=0-5.

Abstract: A data accessing method of a switch for transmitting data packets between a first source node and a first target node and between a second source node and a second target node includes: transmitting a data packet to the switch via at least one of the first communication link and the third communication link and configuring the control unit to store information contained in the data packet into the storage unit; and retrieving the information contained in the data packet from the storage unit via at least one of the second communication link and the fourth communication link. The first source node, the second source node, the first target node and the second target node share the same storage blocks.

Abstract: Methods for isotropic etching at least a portion of a silicon-containing layer on a sidewall of high-aspect-ratio (HAR) apertures formed on a substrate in a reaction chamber are disclosed. The HAR aperture formed by plasma etching a stack of alternating layers of a first silicon-containing layer and a second silicon-containing layer, the second silicon-containing layer is different from the first silicon-containing layer. The method comprising the steps of: a) introducing a fluorine containing etching gas selected from the group consisting of nitrosyl fluoride (FNO), trifluoroamine oxide (F3NO), nitryl fluoride (FNO2) and combinations thereof into the reaction chamber; and b) removing at least a portion of the second silicon-containing layers by selectively etching the second silicon-containing layers versus the first silicon-containing layers with the fluorine containing etching gas to produce recesses between the first silicon-containing layers on the sidewall of the HAR aperture.

Abstract: A switch for transmitting data packets between at least one source node and at least one target node is provided. The switch includes a storage unit, a control unit, at least one receiving port and at least one transmitting port. The storage unit includes a plurality of storage blocks and configured to cache the data packets. The control unit is configured to manage the storage blocks. The switch receives and caches the data packets transmitted from the at least one source node via the receiving port and transmits the cached data packets to the at least one target node via the transmitting port. A data accessing method adapted for the switch is also provided.

Abstract: A method is described for full waveform inversion using a b-spline projection that produces an earth model that can be used for seismic imaging. The method may be executed by a computer system.

Abstract: A schedule for refreshing a dynamic random access memory (DRAM). Access commands for a DRAM are queued in a command queue. A microcontroller uses a counter to count how many times a rank of the DRAM is refreshed entirely (whether by a one-time per-rank refresh operation or by a series of per-bank refresh operations). When the counter has not reached an upper limit and no access command corresponding to the rank is waiting in the command queue, the microcontroller repeatedly performs the per-rank refresh operation on the rank. Every refresh inspection interval, the microcontroller decreases the counter by 1.

Abstract: Replacement chemistries for the cC4F8 passivation gas in the Bosch etch process and processes for using the same are disclosed. These chemistries have the formula CxHyFz, with 1?x<7, 1?y?13, and 1?z?13. The replacement chemistries may reduce RIE lag associated with deep silicon aperture etching.

Abstract: The Invention relates to an atmospheric-pressure acetylene carburizing furnace, comprises a reaction chamber, an acetylene intake duct, an exhaust gas duct, a control and metering apparatus, an exhaust gas measurement apparatus, and a computer controller. The computer controller calculates a total amount of carbon in the furnace and an enrichment rate of a workpiece, and adjusts an acetylene intake volume according to the calculation result until process requirements are met. The Invention realizes carburizing with acetylene under atmospheric pressure and reduces the usage costs while improving the equipment efficiency.

Abstract: Replacement chemistries for the cC4F8 passivation gas in the Bosch etch process and processes for using the same are disclosed. These chemistries have the formula CxHyFz, with 1?x<7, 1?y?13, and 1?z?13. The replacement chemistries may reduce RIE lag associated with deep silicon aperture etching.

Abstract: A schedule for refreshing a dynamic random access memory (DRAM). Access commands for a DRAM are queued in a command queue. A microcontroller uses a counter to count how many times a rank of the DRAM is refreshed entirely (whether by a one-time per-rank refresh operation or by a series of per-bank refresh operations). When the counter has not reached an upper limit and no access command corresponding to the rank is waiting in the command queue, the microcontroller repeatedly performs the per-rank refresh operation on the rank. Every refresh inspection interval, the microcontroller decreases the counter by 1.

Abstract: Methods for minimizing plasma-induced sidewall damage during low k etch processes are disclosed. The methods etch the low k layers using the plasma activated vapor of an organofluorine compound having a formula selected from the group consisting of N?C—R; (N?C—)—(R)—(—C?N); Rx[—C?N(Rz)]y; and R(3-a)—N—Ha, wherein a=1-2, x=1-2, y=1-2, z=0-1, x+z=1-3, and each R independently has the formula HaFbCc with a=0-11, b=0-11, and c=0-5.

Abstract: Disclosed are a high-pressure liquid-state or supercritical-state quenching apparatus, comprising a working chamber, a heating device, a cooling device, a vacuum pump set, a storage tank, a buffer tank, a gas booster, a first pressure gauge, and a temperature controller. According to the Invention, vacuum liquid-state or supercritical-state quenching is implemented, which satisfies a quenching requirement of a large workpiece, and can also achieve an effect of high-pressure gas quenching. In addition, clean heat treatment is implemented, which avoids waste gas and waste water pollution, and is energy-saving and environmentally-friendly heat treatment.

Abstract: A schedule for refreshing a dynamic random access memory (DRAM). Access commands for a DRAM are queued in a command queue. First-rank bank-refresh time points and second-rank bank-refresh time points are alternately provided within a refresh inspection interval for the microcontroller to alternately refresh a first rank and a second rank of the DRAM bank-by-bank based on the content contained in the command queue.

Abstract: Replacement chemistries for the cC4F8 passivation gas in the Bosch etch process and processes for using the same are disclosed. These chemistries have the formula CxHyFz, with 1?x<7, 1?y?13, and 1?z?13. The replacement chemistries may reduce RIE lag associated with deep silicon aperture etching.

Abstract: Replacement chemistries for the cC4F8 passivation gas in the Bosch etch process and processes for using the same are disclosed. These chemistries have the formula CxHyFz, with 1 ?x<7, 1?y?13, and 1?z?13. The replacement chemistries may reduce RIE lag associated with deep silicon aperture etching.

Abstract: An I/O circuit includes buffers, a storage module, accumulators, timers, and an arbiter. Each buffer corresponds to a respective virtual channel. Each buffer corresponds to a respective token bucket, and outputs a normal transmission request according to the amount of tokens and an accumulating signal. The storage module stores a lookup table including a plurality of weightings. Each accumulator corresponds to a respective buffer, accumulates a data volume according to the corresponding weighting, and outputs the accumulating signal. Each timer corresponds to a respective buffer, times waiting period after the corresponding buffer outputs the normal transmission request, and outputs a time-out transmission request when the waiting period exceeds a predetermined period. The arbiter receives the time-out transmission requests and the normal transmission requests, and selects one of the buffers from all of the time-out transmission requests and the normal transmission requests.

Abstract: Methods for fabricating a 3D NAND flash memory are disclosed. The method includes the steps of forming a hardmask pattern on the hardmask layer, and using the hardmask pattern to form apertures in the alternating layers by selectively plasma etching the alternating layers versus the hardmask layer using a hydrofluorocarbon etching gas selected from the group consisting of 1,1,1,3,3,3-hexafluoropropane (C3H2F6), 1,1,2,2,3,3-hexafluoropropane (iso-C3H2F6), 1,1,1,2,3,3,3-heptafluoropropane (C3HF7), and 1,1,1,2,2,3,3-heptafluoropropane (iso-C3HF7), wherein the first etching layer comprises a material different from that of the second etching layer.

Abstract: A switch for transmitting data packets between at least one source node and at least one target node is provided. The switch includes a storage unit, a control unit, at least one receiving port and at least one transmitting port. The storage unit includes a plurality of storage blocks and configured to cache the data packets. The control unit is configured to manage the storage blocks. The switch receives and caches the data packets transmitted from the at least one source node via the receiving port and transmits the cached data packets to the at least one target node via the transmitting port. A data accessing method adapted for the switch is also provided.

Abstract: A display panel motherboard and a manufacturing method thereof are provided. The display panel motherboard comprises display panel regions (Q1) spaced apart from each other and precut regions (Q2) adjacent to the display panel regions. The manufacturing method comprises forming an electrical insulating layer (102); and removing at least portions of the electrical insulating layer provided on the precut regions (Q2). The method avoids the problem of other patterns offset on the display panel motherboard caused by the larger internal stress within the electrical insulating layer.

Abstract: An I/O circuit includes buffers, a storage module, accumulators, timers, and an arbiter. Each buffer corresponds to a respective virtual channel. Each buffer corresponds to a respective token bucket, and outputs a normal transmission request according to the amount of tokens and an accumulating signal. The storage module stores a lookup table including a plurality of weightings. Each accumulator corresponds to a respective buffer, accumulates a data volume according to the corresponding weighting, and outputs the accumulating signal. Each timer corresponds to a respective buffer, times waiting period after the corresponding buffer outputs the normal transmission request, and outputs a time-out transmission request when the waiting period exceeds a predetermined period. The arbiter receives the time-out transmission requests and the normal transmission requests, and selects one of the buffers from all of the time-out transmission requests and the normal transmission requests.