Abstract: A nonvolatile memory device includes a shared port block, a plurality of decoded address signals, a read signal, and a read word line. The shared port block includes a shared port communicatively coupled to a block, the block comprising a plurality of memory cells, wherein the shared port is operable to sense a voltage level at each of the plurality of memory cells. The plurality of decoded address signals are communicatively coupled to the block. Each of the plurality of decoded address signals is operable to enable a corresponding one of the plurality of memory cells. The read signal is communicatively coupled to the shared port. The read signal is operable to enable a read operation associated with the block. The read word line signal is communicatively coupled to the shared port block. The read word line signal is operable to enable the read operation.

Abstract: A low profile strip dual in-line memory module (200) includes a passive interposer support structure (90) with patterned openings (91-97) formed between opposing top and bottom surfaces, a plurality of memory chips (D1-D8) attached to the top and bottom surfaces, and vertical solder ball conductors (98) extending through the patterned openings to electrically connect the plurality of memory chips, where each memory chip has an attachment surface facing the passive interposer structure and a patterned array of horizontal conductors (e.g., 82-86) formed on the attachment surface with contact pads electrically connected to the plurality of vertical conductors to define at least one bus conductor that is electrically connected to each memory die in the first and second plurality of memory die.

Abstract: Circuits and methods are provided for compensating an offset voltage measured between a first transistor and a second transistor of a sense amplifier circuit that is configured to sense a bit line signal during a sensing phase. The first transistor and the second transistor are cross-coupled. The first transistor is coupled to a first capacitor and the second transistor is coupled to a second capacitor. The first capacitor is further coupled to the second capacitor, and the first and second capacitors are coupled to a third transistor. The first capacitor applies a first bias voltage to the first transistor during a pre-sensing phase prior to the sensing phase, and the second capacitor applies a second bias voltage to the second transistor during the pre-sensing phase.

Abstract: Circuits and methods are provided for compensating an offset voltage measured between a first transistor and a second transistor of a sense amplifier circuit that is configured to sense a bit line signal during a sensing phase. The first transistor and the second transistor are cross-coupled. The first transistor is coupled to a first capacitor and the second transistor is coupled to a second capacitor. The first capacitor is further coupled to the second capacitor, and the first and second capacitors are coupled to a third transistor. The first capacitor applies a first bias voltage to the first transistor during a pre-sensing phase prior to the sensing phase, and the second capacitor applies a second bias voltage to the second transistor during the pre-sensing phase.

Abstract: A memory device includes a storage unit formed using a substrate, a true bit line BL0 for carrying a bit of data, and a complementary bit line for carrying the bit of data carried by the first true bit line in complementary form. The true bit line is coupled to the storage unit and runs laterally over the substrate. The true bit line and the complementary bit line are adjacent to each other and are vertically stacked above the substrate.

Abstract: A high density, low power, high performance information system, method and apparatus are described in which perpendicularly oriented processor and memory die stacks (130, 140, 150, 160, 170) include integrated deflectable MEMS optical beam waveguides (e.g., 190) at each die edge (e.g., 151) to provide optical communications (184) in and between die stacks by using a beam control method and circuit to maintain and adjust alignment over time by calibrating and updating X and Y counter values stored in deflection registers (541-542) to control DAC circuitry (546, 548) which generates and supplies deflection voltages to charging capacitors (551, 552) connected to deflection electrodes (195-197) positioned on and around each MEMS optical beam waveguide (193-194) to provide two-dimensional alignment and controlled feedback to adjust beam alignment and establish optical communication links between die stacks.

Abstract: A high density, low power, high performance information system, method and apparatus are described in which an integrated circuit apparatus includes a plurality of deflectable MEMS optical beam waveguides (e.g., 190) at each die edge which are each formed with an optical beam structure (193) which is encapsulated by a waveguide beam structure (194) to extend into a deflection cavity (198) and which is surrounded by a plurality of deflection electrodes (195-197) that are positioned on walls of the deflection cavity (198) to provide two-dimensional deflection control of each deflectable MEMS optical beam waveguide in response to application of one or more deflection voltages to provide optical communications (e.g., 184) between different die.

Abstract: A method of manufacturing a microelectronic assembly (100) and a microelectronic device (4100) that include a stacked structure (101). The stacked structure includes a heat spreader (104), at least one die (106) thermally coupled to at least a portion of one side of the heat spreader, at least one other die (108) thermal coupled to at least a portion of an opposite side of the heat spreader, at least one opening (401) in the heat spreader located in a region of between the two die, an insulator (603) disposed in the at least one opening, and electrically conductive material (1308, 1406) in an insulated hole (705) in the insulator. The heat spreader allows electrical communication between the two die through the opening while the insulator isolates the electrically conductive material and the heat spreader from each other.

Abstract: A method and apparatus are provided for error correction of a memory by using a first memory (18), second memory (14), and redundant memory (19) to perform error correction code (ECC) processing on data retrieved from the first memory (18) by using the redundant memory (19) to replace entries in the second memory (14) having repeat addresses, thereby freeing entries in the second memory (14) for use in detecting and managing errors identified by the ECC processing.

Abstract: A nonvolatile memory device includes a shared port block, a plurality of decoded address signals, a read signal, and a read word line. The shared port block includes a shared port communicatively coupled to a block, the block comprising a plurality of memory cells, wherein the shared port is operable to sense a voltage level at each of the plurality of memory cells. The plurality of decoded address signals are communicatively coupled to the block. Each of the plurality of decoded address signals is operable to enable a corresponding one of the plurality of memory cells. The read signal is communicatively coupled to the shared port. The read signal is operable to enable a read operation associated with the block. The read word line signal is communicatively coupled to the shared port block. The read word line signal is operable to enable the read operation.

Abstract: A buffer circuit comprising a capacitor, the capacitor comprising a first terminal and a second terminal, an input signal being coupled to the first terminal; a first buffer stage coupled to the second terminal of the capacitor such that the input signal is capacitively coupled to the first buffer stage; and, a pulse generator coupled to control the first buffer stage, the pulse generator being configured to generate a control pulse corresponding to a hold time of the first buffer stage such that the buffer circuit detects a transition of the input signal during the hold time.

Abstract: The dies of a stacked die integrated circuit (IC) employ the address bus to indicate the particular die, or set of dies, targeted by data on a data bus. During manufacture of the stacked die IC, the IC is programmed with information indicating a width of the address bus. During operation, each die addresses the other dies with addresses having the corresponding width based on this programmed information.

Abstract: A first semiconductor device die is provided having a bottom edge incorporating a notch structure that allows sufficient height and width clearance for a wire bond connected to a bond pad on an active surface of a second semiconductor device die upon which the first semiconductor device die is stacked. Use of such notch structures reduces a height of a stack incorporating the first and second semiconductor device die, thereby also reducing a thickness of a semiconductor device package incorporating the stack.

Abstract: A memory cell includes a first bi-directional resistive element having a cathode coupled to a first power rail and an anode coupled to an internal node, a second bi-directional resistive element having a cathode coupled to the internal node and an anode coupled to a second power rail, and a first transistor having a control electrode coupled to the internal node, a first current electrode coupled to a first bitline, and a second current electrode coupled to a third power rail.

Abstract: A memory cell includes a bi-directional resistive memory element, a first transistor, and a capacitive element. The bi-directional resistive memory element has a first terminal directly connected to a first power rail and a second terminal coupled to an internal node. The first transistor has a control electrode coupled to the internal node, a first current electrode coupled to a first bitline, and a second current electrode coupled to one of the first power rail, a second power rail, or a read wordline. The capacitive element includes a first terminal coupled to the internal node and a second terminal coupled to the read wordline.

Abstract: An optical die probe wafer testing circuit arrangement and associated testing methodology are described for mounting a production test die (157) and surrounding scribe grid (156) to a test head (155) which is positioned over a wafer (160) in alignment with a die under test (163) and surrounding scribe grid (161, 165), such that one or more optical deflection mirrors (152, 154) in the test head scribe grid (156) are aligned with one or more optical deflection mirrors (162, 164) in the scribe grid (161, 165) for the die under test (163) to enable optical die probe testing on the die under test (163) by directing a first optical test signal (158) from the production test die (157), through the first and second optical deflection mirrors (e.g., 152, 162) and to the first die.

Abstract: A memory cell includes a single bi-directional resistive memory element (BRME) having a first terminal directly connected to a first power rail and a second terminal coupled to an internal node; and a first transistor having a control electrode coupled to the internal node, and a first current electrode coupled to a first bitline, and a second current electrode coupled to one of a group consisting of: a read wordline and the first power rail.

Abstract: A charge pump system includes a comparator having a first input coupled to a first reference voltage, a second input coupled to a feedback signal and an output coupled to control operation of a voltage controlled oscillator. The feedback signal is coupled to an output of the charge pump system. An amplifier has a first input coupled to a second reference voltage, a second input coupled to the feedback signal, and an output coupled as input to the voltage controlled oscillator. A gain of the amplifier is lower than a gain of the comparator.

Abstract: A circuit for determining a threshold indication of temperature with respect to a threshold temperature. The circuit includes a timer circuit and a temperature sensor circuit having an counter whose output has a relationship to temperature. At the end of a period determined by the timer circuit, a comparator circuit compares the count of the counter with an indication of the threshold temperature to determine a state of the threshold indication. In response to a change in state of the threshold indication, the circuit changes one of the count time or the counter output's relationship to temperature to provide a hysteresis for the threshold indication.

Abstract: A memory device includes a storage unit formed using a substrate, a true bit line BL0 for carrying a bit of data, and a complementary bit line for carrying the bit of data carried by the first true bit line in complementary form. The true bit line is coupled to the storage unit and runs laterally over the substrate. The true bit line and the complementary bit line are adjacent to each other and are vertically stacked above the substrate.