Patents by Inventor Perry H. Pelley

Perry H. Pelley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FOUR PORT MEMORY WITH MULTIPLE CORES
    Publication number: 20140321185
    Abstract: A memory cluster includes a first block, a second block, a third block, and a fourth block arranged to have a center hole, wherein the first, second, third, and fourth blocks are each have a first port, a second port, a third port, and a fourth port. A first core is in the center hole coupled to the first port of each of the first, second, third, and fourth blocks. A second core is in the center hole coupled to the second port of each of the first, second, third, and fourth blocks. A third core is in the center hole coupled to the third port of each of the first, second, third, and fourth blocks. A fourth core in the center hole coupled to the fourth port of each of the first, second, third, and fourth blocks.
    Type: Application
    Filed: April 30, 2013
    Publication date: October 30, 2014
    Inventors: Perry H. Pelley, Peter J. Wilson
  • Self adjusting reference for input buffer
    Patent number: 8872578
    Abstract: A self adjusting reference for an input buffer including an adjustable voltage shifter, a comparator, and a comparator and adjust circuit. The voltage shifter provides adjustable reference voltages based on a primary reference voltage, including upper, midway, and lower reference voltages. The comparator compares the midway reference voltage with the input voltage to provide an input sense signal indicative of a voltage state of the input voltage. The comparator and adjust circuit increases voltage levels of the reference voltages when the input voltage is in a low voltage state and has a voltage level that is greater than the lower reference voltage, and decreases the voltage levels of the reference voltages when the input voltage is in a high voltage state and has a voltage level that is less than the upper reference voltage.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: October 28, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Perry H. Pelley
  • Multiport memory with matching address and data line control
    Patent number: 8867263
    Abstract: In a multiple port SRAM, a first bit cell is coupled to first and second word lines and a first and second bit line pair. A first data line pair is coupled to the first bit line pair via first switching logic. A second data line pair is coupled to the first bit line pair via second switching logic and to the second bit line pair via third switching logic. If a row address match but not a column address match exists between a first and second access address, the second switching logic selectively connects the second data line pair with the first bit line pair based on a first decoded signal generated from the column address of the second access address and the third switching logic decouples the second data line pair from the second bit line pair.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: October 21, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Perry H. Pelley
  • Multiport memory with matching address control
    Patent number: 8861289
    Abstract: In a multiple port SRAM, a first bit cell is coupled to first and second word lines and a first and second bit line pair. A second bit cell is coupled to the first and second word lines and a third and fourth bit line pair. A first data line pair is coupled to the first bit line pair via first switching logic and to the third bit line pair via second switching logic, and a second data line pair is coupled to the second bit line pair via third switching logic and to the fourth bit line pair via fourth switching logic. If a match exists between at least portions of a first and second access address, a state of the third and forth switching logic is set such that the second bit line pair and the fourth bit line pair remains decoupled from the second data line pair.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: October 14, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Perry H. Pelley
  • Four port memory with multiple cores
    Patent number: 8861243
    Abstract: A memory cluster includes a first block, a second block, a third block, and a fourth block arranged to have a center hole, wherein the first, second, third, and fourth blocks are each have a first port, a second port, a third port, and a fourth port. A first core is in the center hole coupled to the first port of each of the first, second, third, and fourth blocks. A second core is in the center hole coupled to the second port of each of the first, second, third, and fourth blocks. A third core is in the center hole coupled to the third port of each of the first, second, third, and fourth blocks. A fourth core in the center hole coupled to the fourth port of each of the first, second, third, and fourth blocks.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: October 14, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Perry H. Pelley, Peter J. Wilson
  • Synchronous multiple port memory with asynchronous ports
    Patent number: 8848480
    Abstract: A method of operating a multiport memory, which has first and second sets of word lines and bit lines for accessing a memory array, uses a first port and a second port for accesses during a first phase of a master clock and a third port and a fourth port during a second phase of the master clock. Each port has its own port clock, which clocks their own row and column addresses, that is no faster than the master clock. Assuming there is demand for it, four accesses occur for each cycle of the master clock. This has the effect of being able to be sure that a given access is complete within two cycles of the port clocks and can be operated at the rate of one access per cycle of the port clock.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: September 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Perry H. Pelley
  • MULTIPORT MEMORY WITH MATCHING ADDRESS CONTROL
    Publication number: 20140269016
    Abstract: A multiport SRAM has an array of cells, a first port, and a second port. During a period of different row addresses for the ports, the first port uses first word lines and first bit lines. The second port uses second word lines and second bit lines. In response to the second port switching to the same address as the first port to make a row match, the second port and the first port use the first plurality of word lines, but the first port uses the first plurality of bit lines and the second port uses the second plurality of bit lines. If the row match is removed by the first port changing row addresses, a correlation swap is performed so that the first port performs accesses using the second word lines and bit lines and the second port performs accesses using the first word lines and bit lines.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 18, 2014
    Inventor: PERRY H. PELLEY
  • Multi-port register file with multiplexed data
    Patent number: 8837205
    Abstract: A semiconductor memory storage device comprises an array of storage devices including a plurality of rows of the storage devices and a plurality of columns of the storage devices, a first plurality of write ports, a write select signal coupled to the write ports, a plurality of write port address lines coupled as input to each of the write ports, and a first plurality of word line select circuits coupled to receive an address signal and the write select signal for each of the write ports and to provide a single selected write word line signal to a respective one of the rows of the storage devices for one of the first plurality of write ports activated by the write select signal.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: September 16, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Perry H. Pelley, Ravindraraj Ramaraju, Andrew C. Russell
  • Systems and methods for reduced coupling between digital signal lines
    Patent number: 8836371
    Abstract: Methods and systems are disclosed for reduced coupling between digital signal lines. For disclosed embodiments, return-to-zero signaling is dynamically blocked so that high logic levels remain high through entire clock cycles where the next data to be output is also at high logic levels. The dynamically blocked return-to-zero signaling reduces capacitive coupling between digital signal lines, such as clock and data signal lines, that are in close proximity to each other by reducing current flow that would otherwise occur with return-to-zero signaling. The dynamically blocked return-to-zero signaling can be used in a wide variety of environments and implementations.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: September 16, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Perry H. Pelley, James D. Burnett
  • Gate Security Feature
    Publication number: 20140252487
    Abstract: An anti-counterfeiting security circuit is incorporated into an authentic integrated circuit device to induce failure in a counterfeited integrated circuit device by forming the security circuit (e.g., 21, 31, 41, 51) with one or more operatively inert high-k metal gate transistors (e.g., HKMG PMOS 112) having switched or altered work function metal layers (82) where the security circuit defines a first electrical function with the one or more operatively inert high-k metal gate transistors and defines a second different electrical function if the one or more operatively inert high-k metal gate transistors were instead fabricated as operatively functional high-k metal gate transistors of the first polarity type with a work function metal layer of the first polarity type, the security circuit would define a second different electrical function.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Tab A. Stephens, Perry H. Pelley, Michael B. McShane, Paul A. Grudowski
  • SYNCHRONOUS MULTIPLE PORT MEMORY WITH ASYNCHRONOUS PORTS
    Publication number: 20140241100
    Abstract: A memory system includes a multi-port memory having a first port and a second port. First registers and second registers provide first and second addresses, respectively, to the first and second ports. An access controller controls the multi-port memory to launch an access for the valid address provided by the first input registers in response to the first edge of the master clock unless an immediately preceding first edge of the master clock has occurred more recently than the most recent occurrence of the first edge of the first clock and to launch an access for the valid address provided by the second input registers in response to the first edge of the master clock unless an immediately preceding first edge of the master clock has occurred more recently than the most recent occurrence of the first edge of the second clock.
    Type: Application
    Filed: February 28, 2013
    Publication date: August 28, 2014
    Inventor: PERRY H. PELLEY
  • Semiconductor devices with nonconductive vias
    Patent number: 8796855
    Abstract: An electric device with vias that include dielectric structures to prevent conductive material in the vias from electrically connecting conductive structures on a top of the vias with conductive structures on the bottom of the vias. The dielectric structures are formed in selected vias where other vias do not include the dielectric structures.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: August 5, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Perry H. Pelley, Michael B. McShane, Tab A. Stephens
  • Stacked semiconductor devices
    Patent number: 8796822
    Abstract: A stacked semiconductor device includes a first and a second semiconductor device. A first major surface of each of the first and second devices which includes the active circuitry directly face each other. The first major surface of each of the devices includes a beveled edge on at least one edge, and a probe pad which extends onto the beveled edge. A first opening is located between the beveled edges of the first and second devices on a vertical side of the stacked semiconductor device.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: August 5, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Perry H. Pelley, Kevin J. Hess, Michael B. McShane
  • Systems And Methods For Reduced Coupling Between Digital Signal Lines
    Publication number: 20140203841
    Abstract: Methods and systems are disclosed for reduced coupling between digital signal lines. For disclosed embodiments, return-to-zero signaling is dynamically blocked so that high logic levels remain high through entire clock cycles where the next data to be output is also at high logic levels. The dynamically blocked return-to-zero signaling reduces capacitive coupling between digital signal lines, such as clock and data signal lines, that are in close proximity to each other by reducing current flow that would otherwise occur with return-to-zero signaling. The dynamically blocked return-to-zero signaling can be used in a wide variety of environments and implementations.
    Type: Application
    Filed: January 22, 2013
    Publication date: July 24, 2014
    Inventors: Perry H. Pelley, James D. Burnett
  • Transmission system
    Patent number: 8786350
    Abstract: A signal transmission system (10) includes a signal generator circuit (12); a signal regenerator circuit (14) coupled to the signal generator circuit by conductive lines (16, 18). The signal regenerator circuit receives input signals from the signal generator circuit on the conductive lines, and the regenerator circuit includes cascoded transistors (39, 41) and level-shifting circuits (26) coupled to the cascoded transistors. The cascoded transistors amplify the input signals to provide amplified signals. The level-shifting circuits shift a voltage level of the amplified signals to provide level-shifted signals.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: July 22, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Perry H. Pelley
  • MICROELECTRONIC ASSEMBLY HAVING A HEAT SPREADER FOR A PLURALITY OF DIE
    Publication number: 20140197541
    Abstract: A microelectronic assembly (100) and a microelectronic device (4100) include a stacked structure (101). The stacked structure includes a heat spreader (104), at least one die (106) thermally coupled to at least a portion of one side of the heat spreader, at least one other die (108) thermal coupled to at least a portion of an opposite side of the heat spreader, at least one opening (401) in the heat spreader located in a region of between the two die, an insulator (603) disposed in the at least one opening, and electrically conductive material (1308, 1406) in an insulated hole (705) in the insulator. The heat spreader allows electrical communication between the two die through the opening while the insulator isolates the electrically conductive material and the heat spreader from each other.
    Type: Application
    Filed: January 15, 2013
    Publication date: July 17, 2014
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Tab A. STEPHENS, Michael B. McSHANE, Perry H. PELLEY
  • TRANSMISSION SYSTEM
    Publication number: 20140197871
    Abstract: A signal transmission system (10) includes a signal generator circuit (12); a signal regenerator circuit (14) coupled to the signal generator circuit by conductive lines (16, 18). The signal regenerator circuit receives input signals from the signal generator circuit on the conductive lines, and the regenerator circuit includes cascoded transistors (39, 41) and level-shifting circuits (26) coupled to the cascoded transistors. The cascoded transistors amplify the input signals to provide amplified signals. The level-shifting circuits shift a voltage level of the amplified signals to provide level-shifted signals.
    Type: Application
    Filed: January 14, 2013
    Publication date: July 17, 2014
    Inventor: PERRY H. PELLEY
  • MULTIPORT MEMORY WITH MATCHING ADDRESS CONTROL
    Publication number: 20140198590
    Abstract: In a multiple port SRAM, a first bit cell is coupled to first and second word lines and a first and second bit line pair. A second bit cell is coupled to the first and second word lines and a third and fourth bit line pair. A first data line pair is coupled to the first bit line pair via first switching logic and to the third bit line pair via second switching logic, and a second data line pair is coupled to the second bit line pair via third switching logic and to the fourth bit line pair via fourth switching logic. If a match exists between at least portions of a first and second access address, a state of the third and forth switching logic is set such that the second bit line pair and the fourth bit line pair remains decoupled from the second data line pair.
    Type: Application
    Filed: January 14, 2013
    Publication date: July 17, 2014
    Inventor: PERRY H. PELLEY
  • MULTIPORT MEMORY WITH MATCHING ADDRESS AND DATA LINE CONTROL
    Publication number: 20140198561
    Abstract: In a multiple port SRAM, a first bit cell is coupled to first and second word lines and a first and second bit line pair. A first data line pair is coupled to the first bit line pair via first switching logic. A second data line pair is coupled to the first bit line pair via second switching logic and to the second bit line pair via third switching logic. If a row address match but not a column address match exists between a first and second access address, the second switching logic selectively connects the second data line pair with the first bit line pair based on a first decoded signal generated from the column address of the second access address and the third switching logic decouples the second data line pair from the second bit line pair.
    Type: Application
    Filed: January 14, 2013
    Publication date: July 17, 2014
    Inventor: PERRY H. PELLEY
  • BUS SIGNAL ENCODED WITH DATA AND CLOCK SIGNALS
    Publication number: 20140197976
    Abstract: A CODEC includes a transmission path between an encoder and a decoder. The encoder receives bits of data in a first form in which each bit of the data is represented by switching between first and second logic states and no voltage change between consecutive bits of the same logic state and serially transmits the bits in a second form in which the first logic state is maintained at a high voltage, the second logic state is maintained at a low voltage, and an intermediate voltage is maintained between consecutive bits. The decoder receives the bits in the second form and derives a clock from the occurrences of the intermediate voltage. The clock, repetitively, is maintained at a logic high, then switches directly from the logic high to a logic low, then is maintained at the logic low, and then switches directly between the logic low and the logic high.
    Type: Application
    Filed: January 11, 2013
    Publication date: July 17, 2014
    Inventor: PERRY H. PELLEY