Abstract: Systems, methods, and non-transitory media are presented that provide for improving color accuracy. An electronic display includes a display region having multiple pixels each having multiple subpixels. The electronic device also includes a display pipeline coupled to the electronic display. The display pipeline is configured to receive image data and perform white point compensation on the image data to compensate for a current drop in the display to cause the display to display a target white point when displaying white. The display pipeline also is configured to correct white point overcompensation on the image data to reduce possible oversaturation of non-white pixels using the white point compensation. Finally, the display pipeline is configured to output the compensated and corrected image data to the electronic display to facilitate displaying the compensated and corrected image data on the display region.

Abstract: One embodiment describes an electronic display that includes display driver circuitry that displays at least a first image frame and a second image frame on the electronic device using a first display pixel and a second display pixel. A timing controller of the electronic display determines at least a first insertion time for a first intra-frame pause for the first image frame and a second insertion time for a second intra-frame pause for the second image frame, which pause rendering of image data to allow the touch sensing circuitry to detect user interaction. The insertion times for the first and second intra-frame pauses are varied from one another by a determined step size.

Abstract: Systems, methods, and non-transitory media are presented that provide for improving color accuracy. An electronic display includes a display region having multiple pixels each having multiple subpixels. The electronic device also includes a display pipeline coupled to the electronic display. The display pipeline is configured to receive image data and perform white point compensation on the image data to compensate for a current drop in the display to cause the display to display a target white point when displaying white. The display pipeline also is configured to correct white point overcompensation on the image data to reduce possible oversaturation of non-white pixels using the white point compensation. Finally, the display pipeline is configured to output the compensated and corrected image data to the electronic display to facilitate displaying the compensated and corrected image data on the display region.

Abstract: An electronic display pipeline may process image data for display on an electronic display. The electronic display pipeline may include burn-in compensation statistics collection circuitry and burn-in compensation circuitry. The burn-in compensation statistics collection circuitry may collect image statistics based at least in part on the image data. The statistics may estimate a likely amount of non-uniform aging of the sub-pixels of the electronic display. The burn-in compensation circuitry may apply a gain to sub-pixels of the image data to account for non-uniform aging of corresponding sub-pixels of the electronic display. The applied gain may be based at least in part on the image statistics collected by the burn-in compensation statistics collection circuitry.

Abstract: Systems and methods for improving operation of an electronic device, which includes an image data processing pipeline that processes input image data. In the processing pipeline, a first processing block generates first processed image data by performing a first function on the input image data; another one or more processing blocks, which includes a second processing block coupled to a first output of the first processing block, generates second processed image data by performing a second function on the first processed image data when received from the first processing block; and a third processing block coupled to the first output and a second output of the other one or more processing blocks performs a third function on the first processed image data when received from the first processing block and performs the third function on the second processed image data when received from the other one or more processing blocks.

Abstract: An electronic device is provided. The electronic device includes a display that is configured to show content that includes a plurality of frames. The plurality of frames includes a first frame that is associated with a pre-transition value. The plurality of frames also includes a second frame that is associated with a current frame value that corresponds to a first luminance. Additionally, the electronic device is configured to determine an overdriven current frame value corresponding to a second luminance that is greater than the first luminance. The electronic device is also configured to display the second frame using the overdriven current frame value.

Abstract: Devices and methods for underrun compensation are provided. By way of example, a technique for underrun compensation includes determining a particular one of a plurality of pixel configurations for a display. When an underrun condition is detected during processing of first image data via an image processing pipeline, at least a portion of requested image data for downstream processing has not yet been provided by an upstream processing component. Accordingly, upon detecting an underrun condition, underrun pixel data for the at least portion of the requested image data is generated, based upon the particular one of the plurality of pixel configurations.

Abstract: Systems and methods for improving operational flexibility of a display pipeline coupled to a display panel that facilitates display of an image by controlling luminance of a display pixel based on display image data. The display pipeline includes a format convert block that receives source image data that indicates target luminance of the display pixel using a source format; determines a color scaling factor associated with a color component in the source image data based on the source format; and generates internal image data that indicates target luminance of the display pixel using an internal format based on application of the color scaling factor to the source image data. Additionally, the display pipeline includes an image data processing block coupled to the format convert block, which processes the internal image data before the display image data is generated to facilitate improving perceived image quality when the image is displayed.

Abstract: Methods and mechanisms for improved performance in a system with power management are described. A system includes a data storage device configured to store data and a display control unit configured to retrieve data from the data storage device. The data storage device may be placed in a reduced power state that results in increased latencies for accessing data within the device. The display control unit is configured to monitor an amount of data available for processing within the display control unit. In response to determining the amount of data has fallen to a threshold level, and in anticipation of a forthcoming data access request, the display control unit conveys an indication that prevents the data storage device from entering or remaining in the reduced power state. Subsequently, the display control unit conveys a request for data to the data storage device which will not be in the reduced power state.

Abstract: Systems, apparatuses, and methods for time shifting tasks in a computing system. A system may include a display control unit configured to process pixels for display. The display control unit may include at least one or more pixel processing pipelines, a control unit, and a pixel buffer. The control unit may be configured to monitor the amount of data in the pixel buffer and set the priority of pixel fetch requests according to the amount of data in the pixel buffer. If the control unit determines that an inter frame period will occur within a given period of time, the control unit may prevent the priority of pixel fetch requests from being escalated if the amount of data in the pixel buffer falls below a threshold. The control unit may also be configured to fill the buffers of the display control unit with as much data as possible during the inter frame period.

Abstract: Systems, apparatuses, and methods for improved power management techniques. An apparatus may include a display control unit, a communication fabric, a memory controller, a memory cache, and a memory. When the memory is power-gated, and the display control unit needs to fetch pixel data, the display control unit may send a wake-up signal to the memory before sending a wake-up signal to the communication fabric. The display control unit may then issue the pixel fetch request later. Additionally, if the display control unit determines that the pixel data has a high probability of being cached, then the display control unit may not send a wake-up signal to the memory, and the display control unit may issue the request earlier. More generally, the display control unit may send wake-up signals to multiple components in a manner which accounts for the wake-up latency of each component.

Abstract: Systems, apparatuses, and methods for driving a split display with multiple display pipelines. Frames for driving a display are logically divided into portions, a first display pipeline drives a first portion of the display, and a second display pipeline drives a second portion of the display. Each display pipeline generates dither noise for each frame in its entirety but only utilizes dither noise for the portion of the frame which is being driven to its respective portion of the display. This approach prevents visual artifacts from appearing at the dividing line between the first and second portions of the display.

Abstract: One embodiment describes an electronic display that includes display driver circuitry that displays at least a first image frame and a second image frame on the electronic device using a first display pixel and a second display pixel. A timing controller of the electronic display determines at least a first insertion time for a first intra-frame pause for the first image frame and a second insertion time for a second intra-frame pause for the second image frame, which pause rendering of image data to allow the touch sensing circuitry to detect user interaction. The insertion times for the first and second intra-frame pauses are varied from one another by a determined step size.

Abstract: In some embodiments, a system includes a memory system, a real-time computing device, and a controller. The real-time computing device stores data within a local buffer having a corresponding storage threshold, where the data satisfies the storage threshold, and where the storage threshold is based on a latency of the memory system and an expected rate of utilization of the data of the local buffer. The controller detects that the memory system should perform an operation, where the memory system is unavailable to the real-time computing device during the operation. In response to detecting that an amount of time for the operation exceeds an amount of time corresponding to the storage threshold, the controller overrides the storage threshold. The controller may override the storage threshold by modifying the storage threshold and by overriding a default priority for access requests of the real-time computing device to the memory system.

Abstract: Systems, apparatuses, and methods for time shifting tasks in a computing system. A system may include a display control unit configured to process pixels for display. The display control unit may include at least one or more pixel processing pipelines, a control unit, and a pixel buffer. The control unit may be configured to monitor the amount of data in the pixel buffer and set the priority of pixel fetch requests according to the amount of data in the pixel buffer. If the control unit determines that an inter frame period will occur within a given period of time, the control unit may prevent the priority of pixel fetch requests from being escalated if the amount of data in the pixel buffer falls below a threshold. The control unit may also be configured to fill the buffers of the display control unit with as much data as possible during the inter frame period.

Abstract: Systems, apparatuses, and methods for improved power management techniques. An apparatus may include a display control unit, a communication fabric, a memory controller, a memory cache, and a memory. When the memory is power-gated, and the display control unit needs to fetch pixel data, the display control unit may send a wake-up signal to the memory before sending a wake-up signal to the communication fabric. The display control unit may then issue the pixel fetch request later. Additionally, if the display control unit determines that the pixel data has a high probability of being cached, then the display control unit may not send a wake-up signal to the memory, and the display control unit may issue the request earlier. More generally, the display control unit may send wake-up signals to multiple components in a manner which accounts for the wake-up latency of each component.

Abstract: Embodiments of an apparatus and method are disclosed that may allow for arbitrating multiple read requests to fetch pixel data from a memory. The apparatus may include a first and a second processing pipeline, and a control unit. Each of the processing pipelines may be configured to generate a plurality of read requests to fetch a respective one of a plurality of portions of stored pixel data. The control unit may be configured to determine a priority for each read request dependent upon display coordinates of one or more pixels corresponding to each of the plurality of portions of stored pixel data, and determine an order for the plurality of read requests dependent upon the determined priority for each read request.

Abstract: Systems, apparatuses, and methods for passing source pixel data through a display control unit. A display control unit includes N-bit pixel component processing lanes for processing source pixel data. When the display control unit receives M-bit source pixel components, wherein ‘M’ is greater than ‘N’, the display control unit may assign the M-bit source pixel components to the N-bit processing lanes. Then, the M-bit source pixel components may passthrough the pixel component processing elements of the display control unit without being modified.

Abstract: Systems, apparatuses, and methods for adjusting the frame refresh rate used for driving frames to a display. A display pipeline is configured to drive a display using a reduced frame refresh rate in certain scenarios. The reduced frame refresh rate may be specified in frame packets which contain configuration data for processing corresponding frames. The display pipeline may drive idle frames to the display to generate the reduced frame refresh rate. When a touch event is detected, the display pipeline may override the reduced frame refresh rate and instead utilize a standard frame refresh rate until all of the frames corresponding to stored frame packets have been processed.

Abstract: A display pipe is configured to generate output frames for display. Additionally, the display pipe may be configured to compress an output frame and write the compressed frame back to memory responsive to detecting static content in successive output frames. The display pipe may also be configured to determine to selectively allow write-back logic to operate when doing so will not cause a pixel underrun to the display. If an underrun might occur, write-back logic is temporarily disabled. If write-back is successful, the display pipe may read the compressed frame from memory for display instead of reading the source frames for compositing and display.