Abstract: In an embodiment, a display pipe is configured to composite one or more frames of images and/or video sequences to generate output frames for display. Additionally, the display pipe may be configured to compress an output frame and write the compressed frame to memory responsive to detecting static content in the output frames is detected. The display pipe may also be configured to read the compressed frame from memory for display instead of reading the frames for compositing and display. In some embodiments, the display pipe may include an idle screen detect circuit configured to monitor the operation of the display pipe and/or the output frames to detect the static content.

Abstract: In an embodiment, a display pipe is configured to composite one or more frames of images and/or video sequences to generate output frames for display. Additionally, the display pipe may be configured to compress an output frame and write the compressed frame to memory responsive to detecting static content in the output frames is detected. The display pipe may also be configured to read the compressed frame from memory for display instead of reading the frames for compositing and display. In some embodiments, the display pipe may include an idle screen detect circuit configured to monitor the operation of the display pipe and/or the output frames to detect the static content.

Abstract: In an embodiment, a system includes hardware optimized for communication to a network display. The hardware may include a display pipe unit that is configured to composite one or more static images and one or more frames from video sequences to form frames for display by a network display. The display pipe unit may include a writeback unit configured to write the composite frames back to memory, from which the frames can be optionally encoded using video encoder hardware and packetized for transmission over a network to a network display. In an embodiment, the display pipe unit may be configured to issue interrupts to the video encoder during generation of a frame, to overlap encoding and frame generation.

Abstract: In an embodiment, a display control unit is configured to transmit read operations to the memory in the system to read image data for processing, and may employ QoS levels with the read operations to ensure that enough data is provided to satisfy the real time display requirements. To determine which QoS level to use for a given read request, the display control unit may be configured to compare an amount of image data in the display control unit (e.g. in various input and/or output buffers in the display control unit) to one or more thresholds. The display control unit may also be configured to dynamically update the thresholds based on a memory stress level in the memory controller.

Abstract: A system and method for efficient dynamic utilization of shared resources. A computing system includes a shared data structure accessed by multiple requestors. Both indications of access requests and indices pointing to entries within the data structure are stored in storage buffers. Each storage buffer maintains at a selected end an oldest stored indication of an access request from a respective requestor. Each storage buffer stores information for the respective requestor in an in-order contiguous manner beginning at the selected end. The indices stored in a given storage buffer are updated responsive to allocating new data or deallocating stored data in the shared data structure. Entries in a storage buffer are deallocated in any order and remaining entries are collapsed toward the selected end to eliminate gaps left by the deallocated entry.

Abstract: A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve and process a top frame packet from the parameter buffer to update one or more of the parameter registers according to the contents of the top frame packet. The control circuit may issue DMA requests to fill the parameter buffer with frame packets transferred from system memory, where the frame packets may be written by an application (or software) executing on a central processing unit.

Abstract: In an embodiment, a display pipe processes video data for visual display. The display pipe may read the video data from memory, and may employ QoS levels with the memory requests to ensure that enough data is provided to satisfy the real time display requirements. The display pipe may include a pixel buffer that stores pixels that are ready for display. Additionally, the display pipe may include one or more input buffers configured to store input video data to be processed and/or one or more output buffers configured to store processed data that is ready for blending into the final pixels for display. The display pipe determine a number of output equivalent pixels in the data in the input and output buffers, and may consider those pixels as well as the ready pixels in the pixel buffer in determining the QoS levels for requests.

Abstract: A display pipe may include a video pipe outputting pixels of a video stream in a first color space, e.g. YCbCr color space. The display pipe may also include a first color space converter to convert the output pixels to a second color space, e.g. to RGB color space, producing a conversion output in which some of the converted output pixels have values that are invalid pixel values in the second color space. The display pipe may also include a blend unit that performs blending operations in the second color space on the converted output pixels to produce a blended conversion output that includes blended pixels in the second color space. A second color space converter in the display pipe may convert the blended pixels from the second color space to the first color space, and correctly display the converted blended pixels on a display screen.

Abstract: A blend unit in a display pipe for processing pixels of video and/or image frames may include multiple blend stages, where each blend stage may include multiple levels for blending pixels according to a blend equation. The blending operation includes blending pixel color values and Alpha values. A multiplication may be performed at each blend level, necessitating Alpha value normalizations in the form of divisions to obtain pixel color values having a specified bit-length. Color value normalizations are not needed when the desired result is an actual color value. In order to reduce the compounding of errors that may result from the introduction of an error at each division, Alpha value normalizations may not be performed at each blend level, carrying the intermediate results forward in fractional form—through one or multiple blend stages—until the end of the blending operation.

Abstract: Video display pipes may terminate with a FIFO (first-in first-out) buffer from which pixels are provided to a display controller to display the pixels on a graphics/video display. The display pipes may frequently process the pixels at a much higher rate than at which the display controller fetches the pixels from the FIFO buffer. In an error-checking only mode, the FIFO may be disabled, and an error-checking (e.g. CRC) block connected in front of the FIFO may receive the pixels processed by the display pipes as fast as the display pipes are capable of processing the pixels. Accordingly, the length of test/simulation time required to perform a test may be determined by the rate at which pixels are generated rather than the rate at which the display controller displays the pixels. It also becomes possible to perform testing/simulation in environments where a display is not supported or is not available.

Abstract: A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame. A control circuit coupled to the buffer and to the one or more processing units may retrieve and process a top frame packet from the parameter buffer to update one or more of the parameter registers according to the contents of the top frame packet. The control circuit may issue DMA requests to fill the parameter buffer with frame packets transferred from system memory, where the frame packets may be written by an application (or software) executing on a central processing unit.

Abstract: A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs.

Abstract: A display pipe may include fetch circuitry and a scaler unit, and registers programmable with information that defines active regions of an image frame. Pixels within the active regions are active pixels to be displayed, pixels outside of the active regions are inactive pixels not to be displayed. The fetch circuitry may retrieve frames from memory, retrieving the active pixels and not retrieving the inactive pixels as defined by the programmed contents of the registers. A scaler unit may produce scaled pixels from the fetched pixels, basing each scaled pixel on a respective corresponding set of pixels. When a given pixel of the respective corresponding set of pixels is an inactive pixel, the scaler unit may assign an estimated value to the given pixel based on one or more active pixels in the respective corresponding set of pixels. The scaler unit may provide the scaled pixels to a blend unit for blending with other pixels.

Abstract: A display pipe unit for processing pixels of video and/or image frames may be injected with dither-noise during processing of the pixels. A random noise generator implemented using Linear Feedback Shift Registers (LFSRs) produces pseudo-random numbers that are injected into the display pipe as dither-noise. Typically, such LFSRs shift freely during operation and the values of the LFSRs are used as needed. By shifting the LFSRs when the values are used to inject noise into newly received data, and not shifting the LFSRs when no new data is received, variations in the delays of receiving the data do not affect the pattern of noise applied to the frames. Therefore, dither-noise can be deterministically injected into the display pipe during testing/debug operation. By updating the LFSRs when new pixel data is available from the host interface instead of updating the LFSRs every cycle, the same dither-noise can be injected for the same received data.

Abstract: A video display pipe used for processing pixels of video and/or image frames may include edge Alpha registers for storing edge Alpha values corresponding to the edges of an image to be translated across a display screen. The edge Alpha values may be specified based on the fractional pixel value by which the image is to be moved in the current frame. The video pipe may copy the column and row of pixels that are in the direction of travel, and may apply the edge Alpha values to the copied column and row. The edge Alpha values may control blending of the additional column and row of the translated image with the adjacent pixels in the original frame, providing the effect of the partial pixel movement, simulating a sub-pixel rate of movement.

Abstract: A system and method for efficient dynamic utilization of shared resources. A computing system includes a shared buffer accessed by two requestors generating access requests. Any entry within the shared buffer may be allocated for use by a first requestor or a second requestor. The storage buffer stores received indications of access requests from the first requestor beginning at a first end of the storage buffer. The storage buffer stores received indications of access requests from the second requestor beginning at a second end of the storage buffer. The storage buffer maintains an oldest stored indication of an access request for the first requestor at the first end and an oldest stored indication of an access request for the second requestor at the second end. The shared buffer deallocates in-order of age from oldest to youngest allocated entries corresponding to a given requestor of the first requestor and the second requestor.

Abstract: A system and method for efficiently processing access requests for a shared resource. A computing system includes a shared memory accessed by multiple requestors. Control logic determines two requestors seek to access a same data block within the shared memory. In response to the determination, a first requestor of the two requestors sends a read request to the shared memory on behalf of the two requestors. The second requestor of the two requestors is prevented from sending a read request. In response to detecting data is returned as a response to the read request generated by the first requestor, both the first requestor and the second requestor retrieve the data. In response to detecting a given requestor of the two requestors generates an indication that it is unable to continue retrieving the same response data, the two requestors return to generating separate, respective read requests.

Abstract: A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs.

Abstract: A system and method for efficiently allocating data in a memory hierarchy. A system includes a memory controller for controlling accesses to a memory and a display controller for processing video frame data. The memory controller includes a cache capable of storing data read from the memory. A given video frame may be processed by the display controller and presented on a respective display screen. During processing, control logic within the display controller sends multiple memory access requests to the memory controller with cache hint information. For the frame data, the cache hint information may alternate between (i) indicating to store frame data read in response to respective requests in the memory cache and (ii) indicating to not store the frame data read in response to respective requests in the memory cache.

Abstract: A system and method for efficiently scheduling memory access requests. A semiconductor chip includes a memory controller for controlling accesses to a shared memory and a display controller for processing frame data. In response to detecting an idle state for the system and the supported one or more displays, the display controller aggregates memory requests for a given display pipeline of one or more display pipelines prior to attempting to send any memory requests from the given display pipeline to the memory controller. Arbitration may be performed while the given display pipeline sends the aggregated memory requests. In response to not receiving memory access requests from the functional blocks or the display controller, the memory controller may transition to a low-power mode.