Patents by Inventor Peter Feeley

Peter Feeley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • TRIM SETTING DETERMINATION FOR A MEMORY DEVICE
    Publication number: 20190139619
    Abstract: The present disclosure includes apparatuses and methods related to a memory system including a controller and an array of memory cells. An example apparatus can include a controller configured to receive operational characteristics of an array of memory cells based on prior operations performed by the array of memory cells, determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells, and send the set of trim settings to the array of memory cells.
    Type: Application
    Filed: November 3, 2017
    Publication date: May 9, 2019
    Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
  • IDENTIFYING ASYNCHRONOUS POWER LOSS
    Publication number: 20190073251
    Abstract: Apparatus having an array of memory cells include a controller configured to read a particular memory cell of a last written page of memory cells of a block of memory cells of the array of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.
    Type: Application
    Filed: November 2, 2018
    Publication date: March 7, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Michael G. Miller, Ashutosh Malshe, Violante Moschiano, Peter Feeley, Gary F. Besinga, Sampath K. Ratnam, Walter Di-Francesco, Renato C. Padilla, JR., Yun Li, Kishore Kumar Muchherla
  • Memory device with dynamic storage mode control
    Patent number: 10223259
    Abstract: A memory system includes: a memory array including a plurality of memory cells, the plurality of memory cells including a plurality of cache memory cells; and a controller coupled to the memory array, the controller configured to: track usage of a first subset of the plurality of cache memory cells operating in a single-level cell (SLC) mode, wherein the tracking includes monitoring for an idle time event; and designate a storage mode for a second subset of the plurality of cache memory cells based on the tracked usage of the first subset, wherein the storage mode determines a storage density to be used for data writes.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: March 5, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Yun Li, Kishore Kumar Muchherla, Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale, Kevin R. Brandt, Sampath K. Ratnam
  • MEMORY DEVICE WITH DYNAMIC CACHE MANAGEMENT
    Publication number: 20190065366
    Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: select a garbage collection (GC) source block storing valid data, calculate a valid data measure for the GC source block for representing an amount of the valid data within the GC source block, and designate a storage mode for an available memory block based on the valid data measure, wherein the storage mode is for controlling a number of bits stored per each of the memory cells for subsequent or upcoming data writes.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Inventors: Kishore Kumar Muchherla, Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale, Kevin R. Brandt, Sampath K. Ratnam, Yun Li, Marc S. Hamilton
  • MEMORY DEVICE WITH DYNAMIC STORAGE MODE CONTROL
    Publication number: 20190065367
    Abstract: A memory system includes: a memory array including a plurality of memory cells, the plurality of memory cells including a plurality of cache memory cells; and a controller coupled to the memory array, the controller configured to: track usage of a first subset of the plurality of cache memory cells operating in a single-level cell (SLC) mode, wherein the tracking includes monitoring for an idle time event; and designate a storage mode for a second subset of the plurality of cache memory cells based on the tracked usage of the first subset, wherein the storage mode determines a storage density to be used for data writes.
    Type: Application
    Filed: October 22, 2018
    Publication date: February 28, 2019
    Inventors: Yun Li, Kishore Kumar Muchherla, Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale, Kevin R. Brandt, Sampath K. Ratnam
  • MEMORY DEVICE WITH DYNAMIC STORAGE MODE CONTROL
    Publication number: 20190065365
    Abstract: A memory system includes: a memory array including a plurality of memory cells, the plurality of memory cells including a plurality of cache memory cells; and a controller coupled to the memory array, the controller configured to: track usage of a first subset of the plurality of cache memory cells operating in a single-level cell (SLC) mode, wherein the tracking includes monitoring for an idle time event; and designate a storage mode for a second subset of the plurality of cache memory cells based on the tracked usage of the first subset, wherein the storage mode determines a storage density to be used for data writes.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Inventors: Yun Li, Kishore Kumar Muchherla, Peter Feeley, Ashutosh Malshe, Daniel J. Hubbard, Christopher S. Hale, Kevin R. Brandt, Sampath K. Ratnam
  • STATE CHANGE IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION
    Publication number: 20180373650
    Abstract: The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host.
    Type: Application
    Filed: August 31, 2018
    Publication date: December 27, 2018
    Inventors: William H. Radke, Victor Y. Tsai, James Cooke, Neal A. Galbo, Peter Feeley
  • Memories including multiple arrays of non-volatile memory cells selectively connected to sense circuitry using different numbers of data lines
    Patent number: 10141056
    Abstract: Memories include first and second arrays of non-volatile memory cells, a first plurality of data lines containing a first number of data lines selectively connected to respective subsets of the first array of non-volatile memory cells, a second plurality of data lines containing a second number of data lines, less than the first number, selectively connected to respective subsets of the second array of non-volatile memory cells, and sense circuitry selectively connected to the first and second pluralities of data lines. The memories are configured, when reading the second array of non-volatile memory cells, to connect the sense circuitry to each data line of the second plurality of data lines, and the memories are configured, when reading the first array of non-volatile memory cells, to connect the sense circuitry to a number of data lines of the first plurality of data lines equal to the second number.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: November 27, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Koji Sakui, Peter Feeley
  • Data signal mirroring
    Patent number: 10108684
    Abstract: Methods, devices, and systems for data signal mirroring are described. One or more methods include receiving a particular data pattern on a number of data inputs/outputs of a memory component, and responsive to determining that a mirrored version of the particular data pattern is received by the memory component, configuring the number of data inputs/outputs to be mirrored.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: October 23, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Michael M. Abraham, Peter Feeley
  • OPERATION OF MIXED MODE BLOCKS
    Publication number: 20180293001
    Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.
    Type: Application
    Filed: April 5, 2017
    Publication date: October 11, 2018
    Inventors: Kishore K. Muchherla, Ashutosh Malshe, Preston A. Thomson, Michael G. Miller, Gary F. Besinga, Scott A. Stoller, Sampath K. Ratnam, Renato C. Padilla, Peter Feeley
  • MEMORY MANAGEMENT
    Publication number: 20180293003
    Abstract: The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.
    Type: Application
    Filed: April 7, 2017
    Publication date: October 11, 2018
    Inventors: Kishore K. Muchherla, Sampath K. Ratnam, Peter Feeley, Michael G. Miller, Preston A. Thomson, Renato C. Padilla, Ashutosh Malshe
  • MEMORIES INCLUDING MULTIPLE ARRAYS OF NON-VOLATILE MEMORY CELLS SELECTIVELY CONNECTED TO SENSE CIRCUITRY USING DIFFERENT NUMBERS OF DATA LINES
    Publication number: 20180286482
    Abstract: Memories include first and second arrays of non-volatile memory cells, a first plurality of data lines containing a first number of data lines selectively connected to respective subsets of the first array of non-volatile memory cells, a second plurality of data lines containing a second number of data lines, less than the first number, selectively connected to respective subsets of the second array of non-volatile memory cells, and sense circuitry selectively connected to the first and second pluralities of data lines. The memories are configured, when reading the second array of non-volatile memory cells, to connect the sense circuitry to each data line of the second plurality of data lines, and the memories are configured, when reading the first array of non-volatile memory cells, to connect the sense circuitry to a number of data lines of the first plurality of data lines equal to the second number.
    Type: Application
    Filed: June 6, 2018
    Publication date: October 4, 2018
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Koji Sakui, Peter Feeley
  • GARBAGE COLLECTION
    Publication number: 20180285258
    Abstract: An example apparatus for garbage collection can include a memory including a plurality of mixed mode blocks. The example apparatus can include a controller. The controller can be configured to write a first portion of sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode. The controller can be configured to write a second portion of sequential host data to the plurality of mixed mode blocks in an XLC mode. The controller can be configured to write the second portion of sequential host data by performing a garbage collection operation. The garbage collection operation can include adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks.
    Type: Application
    Filed: April 4, 2017
    Publication date: October 4, 2018
    Inventors: Kishore K. Muchherla, Sampath K. Ratnam, Peter Feeley, Michael G. Miller, Daniel J. Hubbard, Renato C. Padilla, Ashutosh Malshe, Harish R. Singidi
  • State change in systems having devices coupled in a chained configuration
    Patent number: 10089250
    Abstract: The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: October 2, 2018
    Assignee: Micron Technology, Inc.
    Inventors: William H. Radke, Victor Y. Tsai, James Cooke, Neal A. Galbo, Peter Feeley
  • IDENTIFYING ASYNCHRONOUS POWER LOSS
    Publication number: 20180196705
    Abstract: Apparatus include controllers configured to iteratively program a group of memory cells to respective desired data states; determine whether a power loss to the apparatus is indicated while iteratively programming the group of memory cells; and if a power loss to the apparatus is indicated, to change the desired data state of the particular memory cell before continuing with the programming. Apparatus further include controllers configured to read a particular memory cell of a last written page of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and to mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.
    Type: Application
    Filed: March 5, 2018
    Publication date: July 12, 2018
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Michael G. Miller, Ashutosh Malshe, Violante Moschiano, Peter Feeley, Gary F. Besinga, Sampath K. Ratnam, Walter Di-Francesco, Renato C. Padilla, JR., Yun Li, Kishore Kumar Muchherla
  • Methods for backup sequence using three transistor memory cell devices
    Patent number: 10014053
    Abstract: Methods for a backup sequence includes reading first data from a first data memory to a page buffer, copying the first data from the page buffer to a backup page comprising three transistor memory cell devices, erasing the first data memory, programming the first data from the page buffer to a second data memory, and erasing the backup page.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: July 3, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Koji Sakui, Peter Feeley
  • Remapping in a memory device
    Patent number: 10007465
    Abstract: Methods of operating a memory device, and memory devices and systems so configured, include receiving a first address range for programming user data to a first range of physical memory addresses of a memory device, receiving a second address range for programming associated metadata to a second range of physical memory addresses of the memory device, determining whether the first address range is contiguous with the second address range, maintaining the second range of physical memory addresses for programming the metadata when it is determined that the second address range is contiguous with the first address range, and, when it is determined that the second address range is not contiguous with the first address range, remapping the second address range to a third range of physical memory addresses of the memory contiguous with the first range of physical memory addresses for programming the metadata.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: June 26, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Lance Dover, Jim Cooke, Peter Feeley
  • HYBRID FUEL SYSTEM
    Publication number: 20180149096
    Abstract: A hybrid fuel supply system for diesel and other fuel injected internal combustion engines; the system including separate liquid fuel and compressed hydrogen gas sources; and wherein a hydrogen gas supply module calculates of “maps” instant liquid fuel requirements based on engine size and capacity and at least one parameter output from the engine's control unit (ECU) to derive an instant volume of hydrogen gas for addition to the engine's fuel injection system.
    Type: Application
    Filed: April 27, 2016
    Publication date: May 31, 2018
    Applicant: GHP IP PTY LTD
    Inventors: Elaine JOHNS, Peter FEELEY
  • Packet deconstruction/reconstruction and link-control
    Patent number: 9929967
    Abstract: The present disclosure includes methods, devices, and systems for packet processing. One method embodiment for packet flow control includes deconstructing a transport layer packet into a number of link-control layer packets, wherein each of the link-control layer packets has an associated sequence number, communicating the number of link-control layer packets via a common physical connection for a plurality of peripheral devices, and limiting a number of outstanding link-control layer packets during the communication.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: March 27, 2018
    Assignee: Micron Technology, Inc.
    Inventors: William H. Radke, Victor Y. Tsai, Peter Feeley, Neal A. Galbo, Robert N. Leibowitz
  • MEMORY DEVICES AND ELECTRONIC SYSTEMS HAVING A HYBRID CACHE WITH STATIC AND DYNAMIC CELLS, AND RELATED METHODS
    Publication number: 20180081543
    Abstract: A memory device having a memory controller is configured to operate a hybrid cache including a dynamic cache including XLC blocks and a static cache including the SLC blocks. The memory controller is configured to disable at least one of the static cache or the dynamic cache. A method of operating a memory device includes partitioning a memory array into a first portion of SLC blocks and a second portion of XLC blocks, storing at least a portion of host data into the first portion of SLC blocks as a static cache; and storing at least another portion of the host data into the second portion of XLC blocks in an SLC mode as a dynamic cache responsive to a burst of host data being determined to be greater than the static cache can handle. Additional memory devices, methods, and computer systems are also described.
    Type: Application
    Filed: September 19, 2016
    Publication date: March 22, 2018
    Inventors: Kishore K. Muchherla, Ashutosh Malshe, Sampath K. Ratnam, Peter Feeley, Michael G. Miller, Christopher S. Hale, Renato C. Padilla