Patents by Inventor Peter Feeley

Peter Feeley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • GARBAGE COLLECTION
    Publication number: 20190272098
    Abstract: An example apparatus for garbage collection can include a memory including a plurality of mixed mode blocks. The example apparatus can include a controller. The controller can be configured to write a first portion of sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode. The controller can be configured to write a second portion of sequential host data to the plurality of mixed mode blocks in an XLC mode. The controller can be configured to write the second portion of sequential host data by performing a garbage collection operation. The garbage collection operation can include adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks.
    Type: Application
    Filed: May 16, 2019
    Publication date: September 5, 2019
    Inventors: Kishore K. Muchherla, Sampath K. Ratnam, Peter Feeley, Michael G. Miller, Daniel J. Hubbard, Renato C. Padilla, Ashutosh Malshe, Harish R. Singidi
  • Performing an operation on a memory cell of a memory system at a frequency based on temperature
    Patent number: 10403378
    Abstract: A temperature associated with the memory component is determined. A frequency to perform an operation on a memory cell associated with the memory component is determined based on the temperature associated with the memory component. The operation is performed on the memory cell at the determined frequency to transition the memory cell from a state associated with an increased error rate for data stored at the memory cell to another state associated with a decreased error rate for the data stored at the memory cell.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: September 3, 2019
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Sampath K. Ratnam, Vamsi Pavan Rayaprolu, Mustafa N. Kaynak, Peter Feeley, Kishore Kumar Muchherla, Renato C. Padilla, Shane Nowell
  • OPERATION OF MIXED MODE BLOCKS
    Publication number: 20190267105
    Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.
    Type: Application
    Filed: May 15, 2019
    Publication date: August 29, 2019
    Inventors: Kishore K. Muchherla, Ashutosh Malshe, Preston A. Thomson, Michael G. Miller, Gary F. Besinga, Scott A. Stoller, Sampath K. Ratnam, Renato C. Padilla, Peter Feeley
  • REDUNDANT ARRAY OF INDEPENDENT NAND FOR A THREE-DIMENSIONAL MEMORY ARRAY
    Publication number: 20190258544
    Abstract: The present disclosure includes a redundant array of independent NAND for a three dimensional memory array. A number of embodiments include a three-dimensional array of memory cells, wherein the array includes a plurality of pages of memory cells, a number of the plurality of pages include a parity portion of a redundant array of independent NAND (RAIN) stripe, and the parity portion of the RAIN stripe in each respective page comprises only a portion of that respective page.
    Type: Application
    Filed: May 3, 2019
    Publication date: August 22, 2019
    Inventors: Jung Sheng Hoei, Sampath K. Ratnam, Renato C. Padilla, Kishore K. Muchherla, Sivagnanam Parthasarathy, Peter Feeley
  • PERFORMING AN OPERATION ON A MEMORY CELL OF A MEMORY SYSTEM AT A FREQUENCY BASED ON TEMPERATURE
    Publication number: 20190252028
    Abstract: A temperature associated with the memory component is determined. A frequency to perform an operation on a memory cell associated with the memory component is determined based on the temperature associated with the memory component. The operation is performed on the memory cell at the determined frequency to transition the memory cell from a state associated with an increased error rate for data stored at the memory cell to another state associated with a decreased error rate for the data stored at the memory cell.
    Type: Application
    Filed: May 29, 2018
    Publication date: August 15, 2019
    Inventors: Sampath K. Ratnam, Vamsi Pavan Rayaprolu, Mustafa N. Kaynak, Peter Feeley, Kishore Kumar Muchherla, Renato C. Padilla, Shane Nowell
  • MEMORY DEVICES AND ELECTRONIC SYSTEMS HAVING A HYBRID CACHE INCLUDING STATIC AND DYNAMIC CACHES, AND RELATED METHODS
    Publication number: 20190250824
    Abstract: Memory devices are disclosed. A memory device may include main memory and a hybrid cache. The hybrid cache includes a dynamic cache including x-level cell (XLC) blocks of non-volatile memory cells shared between the dynamic cache and the main memory. The hybrid cache further includes a static cache including single-level cell (SLC) blocks of non-volatile memory cells. The memory device further includes a memory controller configured to disable at least one of the static cache and the dynamic cache responsive to a workload of the hybrid cache relative to a Total Bytes Written (TBW) Spec for the memory device. Methods of operating a memory device and an electronic system are also described.
    Type: Application
    Filed: April 26, 2019
    Publication date: August 15, 2019
    Inventors: Kishore K. Muchherla, Ashutosh Malshe, Sampath K. Ratnam, Peter Feeley, Michael G. Miller, Christopher S. Hale, Renato C. Padilla
  • PROVIDING RECOVERED DATA TO A NEW MEMORY CELL AT A MEMORY SUB-SYSTEM BASED ON AN UNSUCCESSFUL ERROR CORRECTION OPERATION
    Publication number: 20190250843
    Abstract: At least one data of a set of data stored at a memory cell of a memory component is determined to be associated with an unsuccessful error correction operation. A determination is made as to whether a programming operation associated with the set of data stored at the memory cell has completed. The at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation is recovered in response to determining that the programming operation has completed. Another memory cell of the memory component is identified in response to recovering the at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation. The set of data including the recovered at least one data is provided to the other memory cell of the memory component.
    Type: Application
    Filed: August 10, 2018
    Publication date: August 15, 2019
    Inventors: Sampath K. Ratnam, Vamsi Pavan Rayaprolu, Mustafa N. Kaynak, Sivagnanam Parthasarathy, Kishore Kumar Muchherla, Shane Nowell, Peter Feeley, Qisong Lin
  • Garbage collection
    Patent number: 10380018
    Abstract: An example apparatus for garbage collection can include a memory including a plurality of mixed mode blocks. The example apparatus can include a controller. The controller can be configured to write a first portion of sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode. The controller can be configured to write a second portion of sequential host data to the plurality of mixed mode blocks in an XLC mode. The controller can be configured to write the second portion of sequential host data by performing a garbage collection operation. The garbage collection operation can include adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kishore K. Muchherla, Sampath K. Ratnam, Peter Feeley, Michael G. Miller, Daniel J. Hubbard, Renato C. Padilla, Ashutosh Malshe, Harish R. Singidi
  • MITIGATING A VOLTAGE CONDITION OF A MEMORY CELL IN A MEMORY SUB-SYSTEM
    Publication number: 20190243704
    Abstract: A number of operations that have been performed on one or more memory cells that are proximate to a particular memory cell of the memory component can be identified. A determination as to whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate can be made based on the identified number of operations. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.
    Type: Application
    Filed: July 25, 2018
    Publication date: August 8, 2019
    Inventors: Kishore Kumar Muchherla, Vamsi Pavan Rayaprolu, Peter Feeley, Sampath K. Ratnam, Sivagnanam Parthasarathy, Qisong Lin, Shane Nowell, Mustafa N. Kaynak
  • STORING CRITICAL DATA AT A MEMORY SYSTEM
    Publication number: 20190227870
    Abstract: User data that is to be stored at a memory system can be received. System data associated with the memory system can be identified and the user data and the system data can be stored at the memory system based on an error control operation. A subset of the system data can be identified and the subset of the system data can be stored at the memory system based on another error control operation.
    Type: Application
    Filed: July 6, 2018
    Publication date: July 25, 2019
    Inventors: Vamsi Rayaprolu, Sivagnanam Parthasarathy, Sampath K. Ratnam, Peter Feeley, Kishore Kumar Muchherla
  • Memory devices and electronic systems having a hybrid cache including static and dynamic caches with single and multiple bits per cell, and related methods
    Patent number: 10359933
    Abstract: A memory having a memory controller is configured to operate a hybrid cache including a dynamic cache including x-level cell (XLC) (e.g., multi-level cell (MLC)) blocks and a static cache including single level cell (SLC) blocks. A method of operating the memory includes storing at least a portion of host data into the SLC blocks as static cache; and storing at least another portion of host data into XLC blocks in an SLC mode as dynamic cache responsive to a burst of host data being determined to be greater than the static cache can handle. At least one of the static cache or dynamic cache may be disabled based on monitoring a workload of the hybrid cache relative to a Total Bytes Written (TBW) specification, such as by counting program-erase (PE) cycles of different portions of memory, or responsive to the workload exceeding a predetermined threshold defining one or more switch points.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: July 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kishore K. Muchherla, Ashutosh Malshe, Sampath K. Ratnam, Peter Feeley, Michael G. Miller, Christopher S. Hale, Renato C. Padilla
  • Garbage collection
    Patent number: 10331553
    Abstract: An example apparatus for garbage collection can include a memory including a plurality of mixed mode blocks. The example apparatus can include a controller. The controller can be configured to write a first portion of sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode. The controller can be configured to write a second portion of sequential host data to the plurality of mixed mode blocks in an XLC mode. The controller can be configured to write the second portion of sequential host data by performing a garbage collection operation. The garbage collection operation can include adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: June 25, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kishore K. Muchherla, Sampath K. Ratnam, Peter Feeley, Michael G. Miller, Daniel J. Hubbard, Renato C. Padilla, Ashutosh Malshe, Harish R. Singidi
  • Operation of mixed mode blocks
    Patent number: 10325668
    Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: June 18, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kishore K. Muchherla, Ashutosh Malshe, Preston A. Thomson, Michael G. Miller, Gary F. Besinga, Scott A. Stoller, Sampath K. Ratnam, Renato C. Padilla, Peter Feeley
  • Trim setting determination on a memory device
    Patent number: 10324839
    Abstract: The present disclosure includes apparatuses and methods related to determining trim settings on a memory device. An example apparatus can determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: June 18, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
  • Redundant array of independent NAND for a three-dimensional memory array
    Patent number: 10318378
    Abstract: The present disclosure includes a redundant array of independent NAND for a three dimensional memory array. A number of embodiments include a three-dimensional array of memory cells, wherein the array includes a plurality of pages of memory cells, a number of the plurality of pages include a parity portion of a redundant array of independent NAND (RAIN) stripe, and the parity portion of the RAIN stripe in each respective page comprises only a portion of that respective page.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: June 11, 2019
    Assignee: Micron Technology, Inc
    Inventors: Jung Sheng Hoei, Sampath K. Ratnam, Renato C. Padilla, Kishore K. Muchherla, Sivagnanam Parthasarathy, Peter Feeley
  • Identifying asynchronous power loss
    Patent number: 10303535
    Abstract: Apparatus include controllers configured to iteratively program a group of memory cells to respective desired data states; determine whether a power loss to the apparatus is indicated while iteratively programming the group of memory cells; and if a power loss to the apparatus is indicated, to change the desired data state of the particular memory cell before continuing with the programming. Apparatus further include controllers configured to read a particular memory cell of a last written page of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and to mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: May 28, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Michael G. Miller, Ashutosh Malshe, Violante Moschiano, Peter Feeley, Gary F. Besinga, Sampath K. Ratnam, Walter Di-Francesco, Renato C. Padilla, Jr., Yun Li, Kishore Kumar Muchherla
  • TRIM SETTING DETERMINATION ON A MEMORY DEVICE
    Publication number: 20190138443
    Abstract: The present disclosure includes apparatuses and methods related to determining trim settings on a memory device. An example apparatus can determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells.
    Type: Application
    Filed: November 3, 2017
    Publication date: May 9, 2019
    Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
  • SELECTABLE TRIM SETTINGS ON A MEMORY DEVICE
    Publication number: 20190139618
    Abstract: The present disclosure includes apparatuses and methods related to selectable trim settings on a memory device. An example apparatus can store a number of sets of trim settings and select a particular set of trims settings of the number of sets of trim settings based on desired operational characteristics for the array of memory cells.
    Type: Application
    Filed: November 3, 2017
    Publication date: May 9, 2019
    Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
  • CONFIGURABLE TRIM SETTINGS ON A MEMORY DEVICE
    Publication number: 20190138442
    Abstract: The present disclosure includes apparatuses and methods related to configurable trim settings on a memory device. An example apparatus can include configuring a set of trim settings for an array of memory cells such that the array of memory cells have desired operational characteristics in response to being operated with the set of trim settings.
    Type: Application
    Filed: November 3, 2017
    Publication date: May 9, 2019
    Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
  • TRIM SETTING DETERMINATION FOR A MEMORY DEVICE
    Publication number: 20190139619
    Abstract: The present disclosure includes apparatuses and methods related to a memory system including a controller and an array of memory cells. An example apparatus can include a controller configured to receive operational characteristics of an array of memory cells based on prior operations performed by the array of memory cells, determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells, and send the set of trim settings to the array of memory cells.
    Type: Application
    Filed: November 3, 2017
    Publication date: May 9, 2019
    Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley