Abstract: Memory, memory devices, and a method for a backup sequence are disclosed. In one such memory device, sense circuitry and page buffers are coupled between a three transistor memory cell device and a non-volatile memory device. Enable/disable gates enable selective access to the sense circuitry and page buffers by either the three transistor memory cell device or the non-volatile memory device.

Abstract: The present disclosure includes methods, devices, and systems for adjusting sensing voltages in devices. One or more embodiments include memory cells, and a controller configured to perform a sense operation on the memory cells using a sensing voltage to determine a quantity of the memory cells having a threshold voltage (Vt) greater than the sensing voltage and adjust a sensing voltage used to determine a state of the memory cells based, at least partially, on the determined quantity of memory cells.

Abstract: The present disclosure includes methods, devices, and systems for packet processing. One method embodiment for packet flow control includes deconstructing a transport layer packet into a number of link-control layer packets, wherein each of the link-control layer packets has an associated sequence number, communicating the number of link-control layer packets via a common physical connection for a plurality of peripheral devices, and limiting a number of outstanding link-control layer packets during the communication.

Abstract: The present disclosure includes methods, devices, and systems for object oriented memory in solid state devices. One embodiment of a method for object oriented memory in solid state devices includes accessing a defined set of data as a single object in an atomic operation manner, where the accessing is from a source other than a host. The embodiment also includes storing the defined set of data as the single object in a number of solid state memory blocks as formatted by a control component of a solid state device that includes the number of solid state memory blocks.

Abstract: The disclosure is related to memory arrays and methods. One such memory array has a substantially vertical pillar. A memory cell adjacent to the pillar where the pillar has a first size has a greater channel length than a memory cell adjacent to the pillar where the pillar has a second size larger than the first size.

Abstract: The present disclosure includes apparatuses and methods for sensing data stored in memory. A number of embodiments include an array of memory cells, and a controller coupled to the array and configured to sense a page of memory cells coupled to an activated access line by pre-charging only a single subset of a number of data lines coupled to the page, wherein more than two subsets of data lines are coupled to the page and the single subset is coupled to those memory cells storing at least a portion of a single sector of data of the page, and sensing the single subset of the number of data lines to determine the at least a portion of the single sector of data.

Abstract: The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device.

Abstract: The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an array of memory cells and control circuitry having sense circuitry coupled to the array. The control circuitry is configured to determine changes in threshold voltages (Vts) associated with the memory cells without using a reference cell, and adjust the sense circuitry based on the determined changes and without using a reference cell.

Abstract: Methods for memory cell coupling compensation and apparatuses configured to perform the same are described. One or more methods for memory cell coupling compensation includes determining a state of a memory cell using a voltage that is changed in accordance with a first memory cell coupling compensation voltage, performing an error check on the state of the memory cell, and determining the state of the memory cell using a voltage that is changed in accordance with a second memory cell coupling compensation voltage in response to the error check failing.

Abstract: The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host.

Abstract: The present disclosure includes methods, devices, and systems for booting in systems having devices coupled in a chained configuration. One or more embodiments include a host and a number of devices coupled to the host in a chained configuration, wherein at least one of the number of devices is a bootable device and the at least one bootable device is not directly coupled to the host.

Abstract: Devices and methods of programming memory cells, both SLC and MLC, such as to reduce charge-storage structure to charge-storage structure coupling, are shown and described. Programming of memory cells can include comparing a first page of data to a second page of data, and further programming cells corresponding to the first page of data that will not likely be affected by coupling from programming the second page of data.

Abstract: The present disclosure includes methods, devices, and systems for packet processing. One method embodiment for packet flow control includes deconstructing a transport layer packet into a number of link-control layer packets, wherein each of the link-control layer packets has an associated sequence number, communicating the number of link-control layer packets via a common physical connection for a plurality of peripheral devices, and limiting a number of outstanding link-control layer packets during the communication.

Abstract: Memory devices, connectors and methods for terminating an operation are provided, including a memory device configured to terminate an internal operation such as a programming or erase operation responsive to receiving a signal during removal of the memory device from a connector, such as a socket. The memory device may be configured to generate the removal signal, such as by including a dedicated removal terminal. The memory card may respond to the signal by terminating a programming or erase operation before power is lost. The removal terminal may have a dimension that is different from a dimension of a power terminal. Alternatively, the connector may be configured to generate a signal that causes a host to terminate programming or erase operations prior to memory card removal, such as by including a switch that is actuated when the memory device moves to a pre-power loss position.

Abstract: The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an array of memory cells and control circuitry having sense circuitry coupled to the array. The control circuitry is configured to determine changes in threshold voltages (Vts) associated with the memory cells without using a reference cell, and adjust the sense circuitry based on the determined changes and without using a reference cell.

Abstract: The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device.

Abstract: The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include an array of memory cells and control circuitry coupled to the array. The control circuitry is configured to perform a number of sense operations on the memory cells using a number of sensing voltages to determine soft data associated with a target state of the memory cells, and adjust a sensing voltage used to determine the target state based, at least partially, on the determined soft data.

Abstract: Methods for remapping and/or compacting data in memory devices, memory devices, and systems are disclosed. One such method of remapping and/or compacting data includes reducing a first quantity of write operations that are received from a host to a second quantity of write operations for programming to a page of a memory device that are within the specifications of partial page write operations for the memory device. The second quantity of write operations can also remap data that were originally intended to be programmed to memory address ranges that conflict with a memory map of the memory device.

Abstract: The present disclosure includes methods, devices, and systems for booting in systems having devices coupled in a chained configuration. One or more embodiments include a host and a number of devices coupled to the host in a chained configuration, wherein at least one of the number of devices is a bootable device and the at least one bootable device is not directly coupled to the host.

Abstract: The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host.