Abstract: A patterned dielectric layer is evaluated by measuring reflectance of a region which has openings. A heating beam may be chosen for having reflectance from an underlying conductive layer that is several times greater than absorptance, to provide a heightened sensitivity to presence of residue and/or changes in dimension of the openings. Reflectance may be measured by illuminating the region with a heating beam modulated at a preset frequency, and measuring power of a probe beam that reflects from the region at the preset frequency. Openings of many embodiments have sub-wavelength dimensions (i.e. smaller than the wavelength of the heating beam). The underlying conductive layer may be patterned into links of length smaller than the diameter of heating beam, so that the links float to a temperature higher than a corresponding temperature attained by a continuous trace that transfers heat away from the illuminated region by conduction.

Abstract: A TCO layer structure and methods of processing the layer in thin film materials including other layers such as layers of CIGS material are disclosed herein. According to one aspect, the invention includes a novel design of a multi-layer TCO structure. According to another aspect, the TCO layer structure of the invention is comprised of inexpensive materials and is inexpensive to process and recycle. According to another aspect, the TCO layer structure of the invention is capable of being patterned using photolithographic and etch processing, but is also chemically durable.

Abstract: A processing method described herein provides a method of patterning a MoSe2 and/or Mo material, for example a layer of such material(s) in a thin-film structure. According to one aspect, the invention relates to etch solutions that can effectively etch through Mo and/or MoSe2. According to another aspect, the invention relates to etching such materials when such materials are processed with other materials in a thin film photovoltaic device. According to other aspects, the invention includes a process of etching Mo and/or MoSe2 with selectivity to a layer of CIGS material in an overall process flow. According to still further aspects, the invention relates to Mo and/or MoSe2 etch solutions that are useful in an overall photolithographic process for forming a photovoltaic cell and/or interconnects and test structures in a photovoltaic device.

Abstract: The present invention relates to configuring and wiring together cells in TF PV modules. According to one aspect, cells within the module are adjusted in size to compensate for known process non-uniformity. According to another aspect, the module is divided into a number of smaller series-connected sub-modules that are then wired in parallel. According to another aspect, the module and/or sub-module may have a non-rectangular shape. According to another aspect, lithography and etch processes are preferably used to form interconnects. In another embodiment, contact pads are formed using photolithographic processes, which may be used to mount protect diodes to minimize the risk of damage due to shading or non-uniformity.

Abstract: The present invention relates to configuring and wiring together cells in TF PV modules. According to one aspect, cells are fabricated on one plane on a top surface of a substrate, with wiring patterned on a parallel plane, and vias formed to provide connections between the cell plane and wiring plane. In one embodiment, the wiring plane is on the back surface of the substrate and vias are formed through the substrate. In another embodiment, the wiring plane is on the top surface of the substrate underneath the cell plane and an insulating layer, with the vias formed through the insulating layer. In another embodiment, the cell plane formed on the top surface includes superstrate cells that are illuminated through a transparent substrate, with an insulator between the cell plane and an upper wiring plane. According to another aspect, the heavy bus bar connections in the wiring plane can carry large currents and do not block light impinging on the cells.

Abstract: A method and apparatus measure properties of two layers of a damascene structure (e.g. a silicon wafer during fabrication), and use the two measurements to identify a location as having voids. The two measurements may be used in any manner, e.g. compared to one another, and voids are deemed to be present when the two measurements diverge from each other. In response to the detection of voids, a process parameter used in fabrication of the damascene structure may be changed, to reduce or eliminate voids in to-be-formed structures.

Abstract: A semiconductor wafer having two regions of different dopant concentration profiles is evaluated by performing two (or more) measurements in the two regions, and comparing measurements from the two regions to obtain a reflectivity change measure indicative of a difference in reflectivity between the two regions. Analyzing the reflectivity change measure yields one or more properties of one of the regions if corresponding properties of the other region are known. For example, if one of the two regions is doped and the other region is undoped (e.g. source/drain and channel regions of a transistor), then a change in reflectivity between the two regions can yield one or more of the following properties in the doped region: (1) doping concentration, (2) junction or profile depth, and (3) abruptness (i.e. slope) of a profile of dopant concentration at the junction. In some embodiments, the just-described measurements in the two regions are performed by oscillating a spot of a beam of electromagnetic radiation.

Abstract: A property of a layer is measured by: (1) focusing a heating beam on a region (also called “heated region”) of a conductive layer (2) modulating the power of the heating beam at a predetermined frequency that is selected to be sufficiently low to ensure that at any time the temperature of an optically absorbing layer is approximately equal to (e.g., within 90% of) a temperature of the optically absorbing layer when heated by an unmodulated beam, and (3) measuring the power of another beam that is (a) reflected by the heated region, and (b) modulated in phase with modulation of the heating beam. The measurement in act (3) can be used directly as a measure of the resistance (per unit area) of a conductive pad formed by patterning the conductive layer. Change in measurement across regions indicates a corresponding change in resistance of the layer.

Abstract: A semiconductor wafer having two regions of different dopant concentration profiles is evaluated by performing two (or more) measurements in the two regions, and comparing measurements from the two regions to obtain a reflectivity change measure indicative of a difference in reflectivity between the two regions. Analyzing the reflectivity change measure yields one or more properties of one of the regions if corresponding properties of the other region are known. For example, if one of the two regions is doped and the other region is undoped (e.g. source/drain and channel regions of a transistor), then a change in reflectivity between the two regions can yield one or more of the following properties in the doped region: (1) doping concentration, (2) junction or profile depth, and (3) abruptness (i.e. slope) of a profile of dopant concentration at the junction. In some embodiments, the just-described measurements in the two regions are performed by use of only one beam of electromagnetic radiation.

Abstract: A coefficient of a function that relates a measurement from a wafer to a parameter used in making the measurement (such as the power of a beam used in the measurement) is determined. The coefficient is used to evaluate the wafer (e.g. to accept or reject the wafer for further processing), and/or to control fabrication of another wafer. In one embodiment, the coefficient is used to control operation of a wafer processing unit (that may include, e.g. an ion implanter), or a heat treatment unit (such as a rapid thermal annealer).

Abstract: A method and apparatus measure properties of two layers of a damascene structure (e.g. a silicon wafer during fabrication), and use the two measurements to identify a location as having voids. The two measurements may be used in any manner, e.g. compared to one another, and voids are deemed to be present when the two measurements diverge from each other. In response to the detection of voids, a process parameter used in fabrication of the damascene structure may be changed, to reduce or eliminate voids in to-be-formed structures.

Abstract: A method that is sensitive to lattice damage (also called “primary method”) is combined with an additional method that independently measures one of two parameters to which the primary method is sensitive namely dose and energy. In some embodiments, the additional method is sensitive to dose, and in two such embodiments 4PP and SIMS are respectively used to measure dose (independent of energy). In other embodiments, the additional method is sensitive to energy, and in one such embodiment SIMS is used to measure energy (independent of dose). Use of such an additional method resolves an ambiguity in a prior art measurement by the primary method alone. The two methods are used in combination in some embodiments, to determine adjustments needed to match two or more ion implanters to one another or to a reference ion implanter or to a computer model.

Abstract: A method and apparatus measure properties of two layers of a damascene structure (e.g. a silicon wafer during fabrication), and use the two measurements to identify a location as having voids. One of the two measurements is of resistance per unit length. The two measurements may be used in any manner, e.g. compared to one another, and voids are deemed to be present when the two measurements diverge from each other. In response to the detection of voids, a process parameter used in fabrication of the damascene structure may be changed, to reduce or eliminate voids in to-be-formed structures.

Abstract: Heat is applied to a conductive structure that includes one or more vias, and the temperature at or near the point of heat application is measured. The measured temperature indicates the integrity or the defectiveness of various features (e.g. vias and/or traces) in the conductive structure, near the point of heat application. Specifically, a higher temperature measurement (as compared to a measurement in a reference structure) indicates a reduced heat transfer from the point of heat application, and therefore indicates a defect. The reference structure can be in the same die as the conductive structure (e.g. to provide a baseline) or outside the die but in the same wafer (e.g. in a test structure) or outside the wafer (e.g. in a reference wafer), depending on the embodiment.

Abstract: Heat is applied to a conductive structure that includes one or more vias, and the temperature at or near the point of heat application is measured. The measured temperature indicates the integrity or the defectiveness of various features (e.g. vias and/or traces) in the conductive structure, near the point of heat application. Specifically, a higher temperature measurement (as compared to a measurement in a reference structure) indicates a reduced heat transfer from the point of heat application, and therefore indicates a defect. The reference structure can be in the same die as the conductive structure (e.g. to provide a baseline) or outside the die but in the same wafer (e.g. in a test structure) or outside the wafer (e.g. in a reference wafer), depending on the embodiment.

Abstract: Any semiconductor wafer fabrication process may be changed to monitor lateral abruptness of doped layers as an additional step in the wafer fabrication process. In one embodiment, a test structure including one or more doped regions is formed in a production wafer (e.g. simultaneously with one or more transistors) and one or more dimension(s) of the test structure are measured, and used as an estimate of lateral abruptness in other doped regions in the wafer, e.g. in the simultaneously formed transistors. Doped regions in test structures can be located at regularly spaced intervals relative to one another, or alternatively may be located with varying spacings between adjacent doped regions. Alternatively or in addition, multiple test structures may be formed in a single wafer, with doped regions at regular spatial intervals in each test structure, while different test structures have different spatial intervals.

Abstract: An apparatus measures a property of a layer (such as the sheet resistance of a conductive layer) by performing the following method: (1) focusing the heating beam on the heated a region (also called “heated region”) of the conductive layer (2) modulating the power of the heating beam at a predetermined frequency that is selected to be sufficiently low to ensure that at any time the temperature of the optically absorbing layer is approximately equal to (e.g., within 90% of) a temperature of the optically absorbing layer when heated by an unmodulated beam, and (3) measuring the power of another beam that is (a) reflected by the heated region, and (b) modulated in phase with modulation of the heating beam. The measurement in act (3) can be used directly as a measure of the resistance (per unit area) of a conductive pad formed by patterning the conductive layer.

Abstract: Two more measurements are made on the same workpiece, during fabrication. Each measurement may be made employing a different process. The measurements are used together to determine a property of the workpiece. For example, multiple measurements from a first process are used with a predetermined value of the property of interest in a simulator to generate a simulated value of a signal to be measured in a second process. One or more such simulated values and a measured value are used to identify a value of the property of interest. When the workpiece's property is found to not match the specification, a process control parameter used in the workpiece's fabrication is adjusted, thereby to implement process control.

Abstract: A sidewall or other feature in a semiconductor wafer is evaluated by illuminating the wafer with at least one beam of electromagnetic radiation, and measuring intensity of a portion of the beam reflected by the wafer. Change in reflectance between measurements provides a measure of a property of the feature. The change may be either a decrease in reflectance or an increase in reflectance, depending on the embodiment. A single beam may be used if it is polarized in a direction substantially perpendicular to a longitudinal direction of the sidewall. A portion of the energy of the beam is absorbed by the sidewall, thereby to cause a decrease in reflectance when compared to reflectance by a flat region. Alternatively, two beams may be used, of which a first beam applies heat to the feature itself or to a region adjacent to the feature, and a second beam is used to measure an increase in reflectance caused by an elevation in temperature due to heat transfer through the feature.

Abstract: An apparatus measures a property of a layer (such as the sheet resistance of a conductive layer or thermal conductivity of a dielectric layer that is located underneath the conductive layer) by performing the following method: (1) focusing the heating beam on the heated a region (also called “heated region”) of the conductive layer (2) modulating the power of the heating beam at a predetermined frequency that is selected to be sufficiently low to ensure that at least a majority (preferably all) of the generated heat transfers out of the heated region by diffusion, and (3) measuring the power of another beam that is (a) reflected by the heated region, and (b) modulated in phase with modulation of the heating beam. The measurement in act (3) can be used directly as a measure of the resistance (per unit length) of a conductive line formed by patterning the conductive layer.