Patents by Inventor Peter Gregorius
Peter Gregorius has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8914589Abstract: Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access.Type: GrantFiled: September 22, 2008Date of Patent: December 16, 2014Assignee: Infineon Technologies AGInventors: Peter Gregorius, Thomas Hein, Martin Maier, Hermann Ruckerbauer, Thilo Schaffroth, Ralf Schedel, Wolfgang Spirkl, Johannes Stecker
-
Patent number: 8495310Abstract: A system and method utilize a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated with a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access. In some embodiments, a plurality of memory devices may be arranged in a memory package in a stacked die memory configuration.Type: GrantFiled: September 22, 2008Date of Patent: July 23, 2013Assignee: Qimonda AGInventors: Peter Gregorius, Thomas Hein, Martin Maier, Hermann Ruckerbauer, Thilo Schaffroth, Ralf Schedel, Wolfgang Spirkl, Johannes Stecker
-
Patent number: 8392779Abstract: A method of adjusting an interface voltage includes transferring data between a memory device and a controller, and detecting whether an error occurred in the transfer of data. An interface voltage of at least one of the memory device and the controller is adjusted based on the detection.Type: GrantFiled: April 25, 2008Date of Patent: March 5, 2013Assignee: Qimonda AGInventors: Andreas Schneider, Markus Balb, Thomas Hein, Christoph Bilger, Martin Brox, Peter Gregorius, Michael Richter
-
Patent number: 8305834Abstract: A semiconductor memory including a plurality of memory banks disposed on an integrated circuit, each memory bank including an array of memory cells, wherein a first portion of memory cells of the plurality of memory banks has a first access speed and a second portion of memory cells of the plurality of memory banks has a second access speed, wherein the first access speed is different from the second access speed.Type: GrantFiled: February 23, 2010Date of Patent: November 6, 2012Assignee: Qimonda AGInventors: Michael Richter, Markus Balb, Christoph Bilger, Martin Brox, Peter Gregorius, Thomas Hein, Andreas Schneider
-
Patent number: 8271827Abstract: A system including a central processing unit, a first memory channel being configured to couple the central processing unit to a first semiconductor memory unit, wherein the first memory channel is configured to be clocked with a first clock frequency, and a second memory channel being configured to couple the central processing unit to a second semiconductor memory unit, wherein the second memory channel is configured or configurable to be clocked with a second clock frequency smaller than the first clock frequency.Type: GrantFiled: December 10, 2007Date of Patent: September 18, 2012Assignee: QimondaInventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
-
Patent number: 8161219Abstract: Distributed command and address bus architecture for memory modules and circuit boards is described. In one embodiment, a memory module includes a plurality of connector pins disposed on an edge of a circuit board, the plurality of connector pins comprising first pins coupled to a plurality of data bus lines, second pins coupled to a plurality of command and address bus lines, wherein the second pins are disposed in a first and a second region, wherein a portion of the first pins is disposed between the first and the second regions.Type: GrantFiled: December 4, 2008Date of Patent: April 17, 2012Assignee: Qimonda AGInventors: Michael Bruennert, Peter Gregorius, Georg Braun, Andreas Gärtner, Hermann Ruckerbauer, George William Alexander, Johannes Stecker
-
Patent number: 8144755Abstract: The invention provides a method and an apparatus for determining a skew of each data bit of an encoded data word received by a receiver via an interface from a transmitter comprising the steps of performing an error check and correction of the received and sampled encoded data word to calculate an error corrected encoded data word corresponding to the encoded data word transmitted by the transmitter, and correlating a sequence of error corrected encoded data words with the sampled encoded data words to determine a skew of each data bit of said received encoded data words.Type: GrantFiled: November 29, 2007Date of Patent: March 27, 2012Inventors: Michael Bruennert, Christoph Bilger, Peter Gregorius, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
-
Patent number: 8125812Abstract: Method and device for transmitting outgoing useful signals and an outgoing clock signal. Useful signals and a clock signal are transmitted from a transmitter via a first line pair and a second line pair to a receiver. A first useful signal is transmitted in the form of a modulated difference between the electrical potentials of the first line pair. A second useful signal is transmitted in the form of a modulated difference between the electrical potentials of the second line pair. The clock signal is transmitted in the form of a modulated difference between the average value of the potentials of the first line pair and the average value of the potentials of the second line pair.Type: GrantFiled: March 31, 2008Date of Patent: February 28, 2012Assignee: Qimonda AGInventors: Martin Streibl, Peter Gregorius, Ralf Schledz
-
Patent number: 8120958Abstract: The multi-die memory comprises a first die and a second die. The first die comprises a first group of memory banks, and the second die comprises a second group of memory banks. The first group of memory banks and the second group of memory banks are coupled to a common memory interface. The common memory interface couples the multi-die memory with an internal connection.Type: GrantFiled: December 24, 2007Date of Patent: February 21, 2012Assignee: Qimonda AGInventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
-
Patent number: 8108643Abstract: In a semiconductor memory system having a loop forward architecture, the command, address and write data stream and the separate read data stream in form of protocol-based frames transmitted to/from memory chips in the following order: memory controller to the first memory chip, to the second memory chip, to the third memory chip and to the fourth memory chip and the read data stream is transferred from the fourth memory chip to the memory controller. With each command usually one of four memory chips is accessed for data processing, while three of four memory chips have only to fulfil a simple re-drive of CAwD stream and read data stream. By separately transferring a rank select signal not embedded in the frame from the memory controller to each memory chip a lot of more flexibility for these tasks can be achieved.Type: GrantFiled: July 29, 2005Date of Patent: January 31, 2012Assignee: Qimonda AGInventors: Paul Wallner, Peter Gregorius
-
Patent number: 8041865Abstract: A memory system includes a number of integrated circuit chips coupled to a bus. Each of the integrated circuit chips has an input/output node coupled to the bus, the input/output node having a programmable on-die termination resistor. The input/output node of one of the integrated circuit chips is accessed via the bus. The programmable on-die termination resistor of each of the integrated circuit chips is independently set to a termination resistance. The termination resistance is determined by a transaction type and which of the plurality memory devices is being accessed, which information can be transmitted over a separate transmission control bus.Type: GrantFiled: August 4, 2008Date of Patent: October 18, 2011Assignee: Qimonda AGInventors: Michael Bruennert, Peter Gregorius, Georg Braun, Andreas Gaertner, Hermann Ruckerbauer, George Alexander, Johannes Stecker
-
Patent number: 8031539Abstract: In an embodiment, a memory device comprises a clock generating unit being configured to generate a read clock signal, the clock generating unit being connected to a first clock signal contact configured to send the read clock signal, and the clock generating unit being connected to data signal contacts being configured to send data signals, the memory device being configured to send the data signals in a phase and frequency accurate (source synchronous) manner with regard to the read clock signal.Type: GrantFiled: October 9, 2008Date of Patent: October 4, 2011Assignee: Qimonda AGInventor: Peter Gregorius
-
Patent number: 8015438Abstract: The invention provides a memory circuit comprising a plurality of storage cells for storing data and redundant spare storage cells for replacing defective storage cells, and a memory access logic for accessing said storage cells connected to a replacement setting register which is writeable during operation of said memory circuit to store replacement settings.Type: GrantFiled: November 29, 2007Date of Patent: September 6, 2011Assignee: Qimonda AGInventors: Michael Bruennert, Christoph Bilger, Peter Gregorius, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
-
Publication number: 20110205828Abstract: A semiconductor memory including a plurality of memory banks disposed on an integrated circuit, each memory bank including an array of memory cells, wherein a first portion of memory cells of the plurality of memory banks has a first access speed and a second portion of memory cells of the plurality of memory banks has a second access speed, wherein the first access speed is different from the second access speed.Type: ApplicationFiled: February 23, 2010Publication date: August 25, 2011Applicant: QIMONDA AGInventors: Michael Richter, Markus Balb, Christoph Bilger, Martin Brox, Peter Gregorius, Thomas Hein, Andreas Schneider
-
Patent number: 7928525Abstract: An integrated circuit includes a device stack including: a memory device with a first wireless coupling element, and a semiconductor device with a second wireless coupling element. The first and second wireless coupling elements are arranged face-to-face and are configured to provide a wireless connection between the memory device and the semiconductor device.Type: GrantFiled: April 25, 2008Date of Patent: April 19, 2011Assignee: Qimonda AGInventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
-
Patent number: 7920433Abstract: Method and apparatus that relate to a storage device comprising a plurality of memory cells, an interface device configured to connect the storage device to a host system and configured to transmit signals to read and write data from the host system to the memory cells via a first and second data path, and a logic unit. The logic unit is configured to read and write data from the plurality of memory cells via the second data path, and configured to perform logic operations on data stored in the plurality of memory cells. When performing read and write operations, the first data path excludes the logic unit, and the second data path includes the logic unit. Furthermore, the logic unit is communicatively coupled between the interface device and the plurality of memory cells. Additionally, a method for manufacturing the memory device is provided.Type: GrantFiled: January 9, 2008Date of Patent: April 5, 2011Assignee: Qimonda AGInventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
-
Patent number: 7908232Abstract: A method of training connections in a memory arrangement includes training a connection between a memory section and a receiver portion of a controller for controlling the memory arrangement before or simultaneously with a training of essentially all other connections between elements of the memory arrangement that are to be trained.Type: GrantFiled: August 24, 2007Date of Patent: March 15, 2011Assignee: Qimonda AGInventor: Peter Gregorius
-
Publication number: 20110034045Abstract: Stackable circuit devices include mechanical and electrical connection elements that are optionally disengageable and disconnectable. The mechanical connection elements comprise pairs of complementary male and female plug-in engagement elements respectively arranged at opposite matching positions on top and bottom faces of each device package. The male and female plug-in engagement elements provide a mutual plug-in engagement. The electrical connection elements comprise a plurality of first and second complementary contact elements respectively arranged in opposite and matching positions on either the top or bottom face of each device package. When the circuit devices are stacked, the first contact elements are respectively configured to provide an electrical connection to a complementary matching second contact element of an adjacently plugged in circuit device.Type: ApplicationFiled: August 6, 2009Publication date: February 10, 2011Applicant: QIMONDA AGInventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth
-
Patent number: 7864907Abstract: A data receiver has a sampling unit connected to a data signal input and configured to sample a data signal amplitude and amplify the sampled data signal amplitude to a predetermined value, a sampling clock generator unit connected to the sampling unit and configured to predetermine a sampling clock for the sampling unit, an evaluation unit connected to the sampling unit and configured to determine the time duration required by the sampling unit for amplifying the sampled data signal amplitude to the predetermined value and evaluate the time duration determined, and a control unit connected to the evaluation unit and the sampling clock generator and configured to define the sampling clock on the basis of the evaluation of the time duration determined by the evaluation unit.Type: GrantFiled: April 30, 2007Date of Patent: January 4, 2011Assignee: Qimonda AGInventors: Martin Streibl, Peter Gregorius, Thomas Rickes, Ralf Schledz
-
Patent number: 7848153Abstract: Memory devices and memory modules are disclosed. In one embodiment, a memory device includes a semiconductor substrate having a first edge and a second edge opposed to the first edge. A plurality of memory banks is disposed at a central portion of the semiconductor substrate, each memory bank including a plurality of memory cells. A plurality of input/output contacts is disposed between the first edge and the memory banks. Delay locked loop circuitry is disposed adjacent the first edge. A plurality of address and command contacts is disposed between the second edge and the memory banks.Type: GrantFiled: August 19, 2008Date of Patent: December 7, 2010Assignee: Qimonda AGInventors: Michael Bruennert, Peter Gregorius, Georg Braun, Andreas Gaertner, Hermann Ruckerbauer, George William Alexander, Johannes Stecker