Abstract: Semiconductor memory modules and semiconductor memory systems using the same are described herein. The modules divide a conventional DIMM into a series of separate, smaller memory modules. Each memory module includes at least one semiconductor memory chip arranged on a substrate; CAwD signal input lines arranged on the substrate in a first predetermined line number and connecting one of the semiconductor memory chips to CAwD input signal pins on the substrate; and rD signal output lines arranged on the substrate in a second predetermined line number and connecting the one or a last semiconductor memory to a second number of rD output signal pins of the substrate. In a semiconductor memory system including the semiconductor memory modules, each memory module is separately connected to a memory controller by the CAwD signal input lines and the rD signal output lines in a respective point-to-point fashion.

Abstract: There is provided a method of operating a memory device comprising at least one memory module, a corresponding memory module and a memory device comprising the at least one memory module. It is proposed that in the memory module (100a, 100b, 100c, 100d) a command and write data signal (CA, WD) is received and a read data signal (RD) is transmitted from the memory module (100a, 100b, 100c, 100d). Further, an input clock signal (CLK) is received in the memory module (100a, 100b, 100c, 100d) and is regenerated by means of a clock synthesizer unit (150) of the memory module (100a, 100b, 100c, 100d) to produce a regenerated input clock signal of the memory module (100a, 100b, 100c, 100d). The read data signal (RD) transmitted from the memory module (100a, 100b, 100c, 100d) is synchronized to the regenerated input clock signal of the memory module (100a, 100b, 100c, 100d). For this purpose, the clock synthesizer unit (150) preferably comprises a phase-locked loop.

Abstract: A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.

Abstract: A device for setting a clock delay is proposed, wherein delayed output clock signals are generated with the aid of delaying means by delaying an input clock signal. The delaying means are configured to provide several differently delayed clock signals simultaneously. The device is configured to generate the at least one output clock signal depending on the differently delayed clock signals with a settable phase relationship to the non-delayed input clock signal, wherein the phase relationship is settable independently of the delay provided by the delaying means. It is particularly provided that the phase relationship between the delayed output clock signal and the non-delayed input clock signal is automatically controlled to a desired phase relationship independently of the delay supplied by the delaying means.

Abstract: A method and a device for reconstructing data, clocked at a symbol rate, from a signal which has been distorted by transmission of a transmission link, are disclosed. The method or respectively, the device, being predominantly performed or implemented, respectively, by means of digital circuit technology in order to improve the quality of the data recovery. The method includes amplifying the signal amplitude attenuated by the transmission; filtering high-frequency interference frequencies above the symbol rate; discretizing the analog signal by means of an analog/digital converter; performing a cable approximation by means of a digitally implemented cable approximation filter in order to obtain an equalized signal; and recovering the data from the equalized signal by means of a phase-locked loop.

Abstract: A memory system and method is discussed. The memory system includes a memory controller and at least one memory module on which a certain number of semiconductor memory chips and connecting lines are arranged in a respectively specified topology. The connecting lines include first connecting lines forming transfer channels for a protocol based transfer of data and command signal streams from the memory controller to at least one of the memory chips on the memory module and from there to the memory controller, respectively. Second connecting lines are routed separately from the memory controller directly to at least one of the memory chips on the memory module for transferring select information to the at least one memory chip separately from the data and command signal streams.

Abstract: A method of training connections in a memory arrangement includes training a connection between a memory section and a receiver portion of a controller for controlling the memory arrangement before or simultaneously with a training of essentially all other connections between elements of the memory arrangement that are to be trained.

Abstract: A semiconductor memory module includes a plurality of semiconductor memory chips and bus signal lines that supply an incoming clock signal and incoming command and address signals to the semiconductor memory chips. A clock signal regeneration circuit and a register circuit are arranged on the semiconductor memory module in a common chip packing connected to the bus signal lines. The clock signal regeneration circuit and the register circuit respectively condition the incoming clock signal and temporarily store the incoming command and address signals, respectively multiply the conditioned clock signal and the temporarily stored command and address signals by a factor of 1:X, and respectively supply to the semiconductor memory chips the conditioned clock signal and the temporarily stored command and address signals.

Abstract: A synchronous signal generator is provided that contains a first and second counting and delay circuit, which both are in a subhierarchical position with respect to a reset signal synchronization/delay circuit. The reset signal synchronization/delay circuit and the first and second counting and delay circuit are triggered by a basic clock signal or a first clock signal derived therefrom to be identical in frequency and phase, and contain counting means whose initial and final counting state are adjustable in order to set, in a clocked fashion, the temporal positions of a first and second load signal that are output by the first counting and delay circuit as well as of a FIFO read clock signal that is output by the second counting and delay circuit and thus adapt them to the temporal requirements of a semiconductor memory system containing the synchronous signal generator.

Abstract: The present invention relates to a method and apparatus for generating an output signal in dependence on a phase difference between two periodic signals. The present invention is particularly useful in phase locked loops and delay locked loops, in which a controllable oscillator or a controllable delay device is controlled on the basis of the phase difference determined by means of phase detection, in such a way that a control signal can be obtained, the phase lag or frequency of which has a firm relationship to the reference signal.

Abstract: A memory device comprising a memory cell array; an input circuit providing drive signals to the memory cell array dependent on externally received command data; an output buffer buffering data read out from the memory cell array; and a timer driving the output buffer such that the buffered data are provided at an output after an adjustable time interval has elapsed, the adjustable time interval beginning with the provision of the drive signals.

Abstract: A control unit is set up to generate and output periodic clock signals, that are in sync with and at the same frequency as a periodic basic clock that is input into it, and periodic control signals, that are likewise in sync with the basic clock, and to turn on/turn off output of at least the clock signal in reaction to an activation/deactivation signal, which is routed to it externally, to a synchronous parallel/serial converter executing synchronization and serialization of a parallel data signal with the basic clock. Whereas output of the clock signal and optionally of the control signals are turned off, immediately after the activation/deactivation signal has assumed its deactivation state, the control unit is able to synchronize turning control signals on again, when the activation/deactivation signal has assumed its activation state.

Abstract: A data receiver has a sampling unit connected to a data signal input and configured to sample a data signal amplitude and amplify the sampled data signal amplitude to a predetermined value, a sampling clock generator unit connected to the sampling unit and configured to predetermine a sampling clock for the sampling unit, an evaluation unit connected to the sampling unit and configured to determine the time duration required by the sampling unit for amplifying the sampled data signal amplitude to the predetermined value and evaluate the time duration determined, and a control unit connected to the evaluation unit and the sampling clock generator and configured to define the sampling clock on the basis of the evaluation of the time duration determined by the evaluation unit.

Abstract: Disclosed is a feed forward clock and data recovery unit for recovering a received serial data bit stream having a feed forward phase tracking unit for tracking of a sampling time to the center of a unit interval of the received data bit stream. The feed forward phase tracking unit can include a sampling phase generation unit, an oversampling unit, a serial-to-parallel-conversion unit, a binary phase detection unit, a loop filter, a finite state machine, a binary rotator, and a data recognition unit for recovery of the received data stream which includes a number of parallel data recognition FIR-Filters. Further, each data recognition FIR-Filter can include a weighting unit for weighting data samples of the deserialized data stream, a summing unit for summing up the weighted data samples, and a comparator unit for comparing the summed up data samples with a threshold value.

Abstract: A feed forward equalizer for analog equalization of a data signal received over a data transmission channel comprising a Master Delay Locked Loop (MDLL) for generating equidistant reference phase signals; a Slave Delay Line (SDL) formed by serial connected Slave Delay Units (SDU), wherein each Slave Delay Unit (SDU) has a Slave Delay Element (SDE) to delay the received data signal with a predetermined delay time (?T) and an analog amplifier which amplifies the delayed output signal of the Slave Delay Element (SDE) with a respective weighting coefficient to generate a weighted delay signal, wherein the analog amplifier is switched transparent in response to a corresponding reference phase signal generated by said Master Delay Locked Loop (M-DLL); and subtracting means for subtracting the weighted delay signals which are selected by means of a multiplexer from the received data signal to generate an equalized output data signal.

Abstract: A method and apparatus for fast digital filtering that requires only filter stages of first and second order. A desired rational filter transfer function is represented as a sum of first and second order intermediate transfer functions. A time dependent input signal is first fed in parallel into a plurality of first and second order intermediate recursive filter stages. Then, the outputs of the intermediate filter stages are summed up to an output filter signal that corresponds to the desired rational filter transfer function. The method and apparatus reduces the amount of calculational effort to the order of O(N), where N denotes the number of sampling points in the time domain, because the digital filtering is based on a discrete recursive convolution in the time domain.

Abstract: A memory device comprising a memory cell array; an input circuit for receiving command data and providing drive signals to the memory cell array; an output buffer for buffering data read out from the memory cell array; and a timer for driving the output buffer such that the buffered data are provided at an output after a predetermined time interval has elapsed, the predetermined time interval beginning with the provision of the drive signals.

Abstract: A method and a device for generating a clock signal (Fout) are provided, wherein a digital phase difference signal (X) is formed depending on a phase difference between a reference clock signal (Fin) and a feedback signal (Ffb) derived from the clock signal (Fout) and wherein the digital phase difference signal (X) is digitally filtered, in order to form a digital filtered phase difference signal (U). A digitally controlled oscillator (5) is activated by a digital control signal dependent on the digital filtered phase difference signal (U) to generate the clock signal (Fout). With a device of this kind clock signals with frequencies in the gigahertz range can be generated with a minimum of analog circuit parts.

Abstract: A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.

Abstract: A method generates a sampling clock signal in a communication block of a memory device having a plurality of communication blocks which are distributed in the memory device. The method includes receiving an input clock signal in the communication block, generating, only in response to the input clock signal, a local clock signal having a predetermined phase relationship with respect to the input clock signal, and generating the sampling clock signal based on the local clock signal.