Patents by Inventor Peter Hsu

Peter Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Layout of memory strap cell
    Patent number: 8704376
    Abstract: A layout structure includes a substrate, a well, a first dopant area, a second dopant area, a first poly region, a third dopant area, a fourth dopant area, and a second poly region. The well is in the substrate. The first poly region is in between the first dopant area and the second dopant area. The second poly region is in between the third dopant area and the fourth dopant area. The first dopant area, the second dopant area, the third dopant area, and the fourth dopant area are in the well. The first dopant area is configured to serve as a source of a transistor and to receive a first voltage value from a first power supply source. The well is configured to serve as a bulk of the transistor and to receive a second voltage value from a second power supply source.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: April 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jacklyn Chang, Evan Yong Zhang, Derek C. Tao, Kuoyuan (Peter) Hsu
  • Sense amplifier
    Patent number: 8692580
    Abstract: An amplifying circuit comprises a bias circuit, a reference circuit, a first circuit, and an amplifying sub-circuit. The bias circuit is configured to provide a bias current. The reference circuit is configured to provide a first differential input based on a reference resistive device and a reference current derived from the bias current. The first circuit is configured to provide a second differential input based on a first current and a first resistance. The amplifying sub-circuit is configured to receive the first differential input and the second differential input and to generate a sense amplifying output indicative of a resistance relationship between the first resistance and a resistance of the reference resistive device.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: April 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Ming Hung, Sung-Chieh Lin, Kuoyuan (Peter) Hsu
  • TWO-PORT SRAM WRITE TRACKING SCHEME
    Publication number: 20140092675
    Abstract: A write tracking control circuit includes an input node, and a first transistor configured to pre-charge a word bit line connected to at least two memory cells. The write tracking control circuit further includes a second transistor configured to pre-charge a read bit line connected to the at least two memory cells. The write tracking control circuit further includes a first delay circuit between the input node and the first transistor, the first delay circuit configured to introduce a first delay time, wherein a gate of the first transistor is connected to the first delay circuit. The write tracking control circuit further includes a second delay circuit between the input node and the second transistor, the second delay circuit configured to introduce a second delay time different from the first delay time, wherein a gate of the second transistor is connected to the second delay circuit.
    Type: Application
    Filed: December 3, 2013
    Publication date: April 3, 2014
    Applicant: TAIWAN SIMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bing WANG, Kuoyuan (Peter) HSU, Derek C. TAO
  • MULTIPLE BITCELLS TRACKING SCHEME SEMICONDUCTOR MEMORY ARRAY
    Publication number: 20140085993
    Abstract: A read tracking system and method for advanced memory devices are provided. The read tracking system and method include tracking multiple tracking bit cells in multiple segments and columns to incorporate device performance variation of bit cells in the memory array. The tracking path mimics the worst-case read path with some built-in margins to sufficiently and efficiently cover the read times of bit cells in a memory array without unnecessarily sacrificing the read speed performance of the memory array. A number of tracking cells may be placed at different segments and both sides of the memory array to cover read time variation across memory array.
    Type: Application
    Filed: September 26, 2012
    Publication date: March 27, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Derek C. TAO, Bing WANG, Kuoyuan (Peter) HSU, Jacklyn Victoria CHANG, Young Suk KIM
  • METAL-VIA FUSE
    Publication number: 20140061851
    Abstract: The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a metal-via fuse. The metal-via fuse and a programming transistor form a one-time programmable (OTP) memory cell. The metal-via fuse has a high resistance and can be programmed with a low programming voltage, which expands the programming window.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 6, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sung-Chieh LIN, Kuoyuan (Peter) HSU, Wei-Li LIAO, Yun-Han CHEN, Chen-Ming HUNG
  • METHOD OF MEMORY WITH REGULATED GROUND NODES
    Publication number: 20140043921
    Abstract: A method of reading data from an accessed memory cell of an accessed column of an accessed section of a memory array includes, in the accessed section, electrically coupling a first voltage source of at least three voltage sources to a corresponding column internal ground node of the accessed column; and electrically coupling the first voltage source to a corresponding column internal ground node of an un-accessed column. The memory array has at least one segment, the at least one segment has at least one section, and each section has at least one column. Each column has at least three switches and a column internal ground node capable of being electrically coupled to at least three voltage sources through a corresponding one of the at least three switches.
    Type: Application
    Filed: October 11, 2013
    Publication date: February 13, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuoyuan (Peter) HSU, Yukit TANG, Derek TAO, Young Seog KIM
  • MEMORY ARCHITECTURE
    Publication number: 20140032835
    Abstract: A write circuit in a memory array includes a global data line, a switching circuit, and a first local data line coupled with the switching circuit and with a first plurality of memory cells. The global data line is configured to receive data to be written to the memory cell from outside of the memory array. The switching circuit is configured to electrically couple the global data line with the first local data line to transfer the data to be written to a memory cell of the first plurality of memory cells to the first local data line. The memory cell of the first plurality of memory cells is configured to receive data on the first local data line.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Kuoyuan (Peter) HSU
  • TRACKING MECHANISM FOR WRITING TO A MEMORY CELL
    Publication number: 20140032871
    Abstract: A circuit includes a tracking write circuit and a write circuit. Various write signals of the write circuit are generated based on tracking signals of the tracking write circuit. The write signals are used in a write operation of a memory cell.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuoyuan (Peter) Hsu, Bing Wang, Derek C. Tao, Yukit Tang, Kai Fan
  • Non-salicide polysilicon fuse
    Patent number: 8625324
    Abstract: The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a non-salicided polysilicon fuse. The non-salicided polysilicon fuse and a programming transistor form a one-time programmable (OTP) memory cell, which can be programmed with a low programming voltage.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: January 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Chieh Lin, David Yen, Chi-Hsu Chiu, Kuoyuan (Peter) Hsu
  • Two-port SRAM write tracking scheme
    Patent number: 8619477
    Abstract: A Static Random Access Memory (SRAM) includes at least two memory cells sharing a read bit line (RBL) and a write bit line (WBL). Each memory cell is coupled to a respective read word line (RWL) and a respective write word line (WWL). A write tracking control circuit is coupled to the memory cells for determining a write time of the memory cells. The write tracking control circuit is capable of receiving an input voltage and providing an output voltage. The respective RWL and the respective WWL of each memory cell are asserted during a write tracking operation.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: December 31, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bing Wang, Kuoyuan (Peter) Hsu, Derek C. Tao
  • Current leakage reduction
    Patent number: 8614927
    Abstract: This description relates to a circuit including a bit line. The circuit further includes at least one memory bank. The at least one memory bank includes at least one memory cell, a first device configured to provide a current path between the bit line and the at least one memory cell when the at least one memory cell is activated, and a second device configured to reduce current leakage between the bit line and the at least one memory cell when the at least one memory cell is deactivated. The circuit further includes a tracking device configured to receive a mirror current substantially equal to a current along the current path, the tracking device configured to have a resistance substantially equal to a cumulative resistance of all memory cells of the at least one memory cell.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: December 24, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Chieh Lin, Kuoyuan (Peter) Hsu, Jiann-Tseng Huang, Wei-Li Liao
  • Tracking capacitive loads
    Patent number: 8605523
    Abstract: A time delay is determined to cover a timing of a memory cell in a memory macro having a tracking circuit. Based on the time delay, a capacitance corresponding to the time delay is determined. A capacitor having the determined capacitance is utilized. The capacitor is coupled to a first data line of a tracking cell of the tracking circuit. A first transition of the first data line causes a first transition of a second data line of the memory cell.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: December 10, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Derek C. Tao, Young Seog Kim, Kuoyuan (Peter) Hsu, Bing Wang, Annie-Li-Keow Lum
  • Recycling charges
    Patent number: 8587991
    Abstract: A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: November 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Young Seog Kim, Kuoyuan (Peter) Hsu, Derek C. Tao, Young Suk Kim
  • WORD LINE DRIVER HAVING A CONTROL SWITCH
    Publication number: 20130301374
    Abstract: A word line driver including a control switch configured to receive a control signal, where the control switch is between a first node configured to receive an operating voltage signal and a second node configured to determine an output of the word line driver. The word line driver further includes a cross-coupled amplifier electrically connected to the second node. The word line driver further includes at least one inverter electrically connected to the cross-coupled amplifier. A semiconductor device including the word line driver and a memory array including at least one electronic fuse.
    Type: Application
    Filed: May 8, 2012
    Publication date: November 14, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Li LIAO, Sung-Chieh LIN, Kuoyuan (Peter) HSU
  • Memory with regulated ground nodes
    Patent number: 8576611
    Abstract: Some embodiments regard a memory array comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; wherein a column of the plurality of columns includes a column ground node; at least two voltage sources configured to be selectively coupled to the column ground node; and a plurality of memory cells having a plurality of internal ground nodes electrically coupled together and to the column ground node.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: November 5, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuoyuan (Peter) Hsu, Yukit Tang, Derek Tao, Young Seog Kim
  • LAYOUT OF MEMORY STRAP CELL
    Publication number: 20130264718
    Abstract: A layout structure includes a substrate, a well, a first dopant area, a second dopant area, a first poly region, a third dopant area, a fourth dopant area, and a second poly region. The well is in the substrate. The first poly region is in between the first dopant area and the second dopant area. The second poly region is in between the third dopant area and the fourth dopant area. The first dopant area, the second dopant area, the third dopant area, and the fourth dopant area are in the well. The first dopant area is configured to serve as a source of a transistor and to receive a first voltage value from a first power supply source. The well is configured to serve as a bulk of the transistor and to receive a second voltage value from a second power supply source.
    Type: Application
    Filed: April 10, 2012
    Publication date: October 10, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jacklyn CHANG, Evan Yong ZHANG, Derek C. TAO, Kuoyuan (Peter) HSU
  • INTEGRATED CIRCUIT STRUCTURE TO RESOLVE DEEP-WELL PLASMA CHARGING PROBLEM AND METHOD OF FORMING THE SAME
    Publication number: 20130256801
    Abstract: During various processing operations, ions from process plasma may be transfer to a deep n-well (DNW) formed under devices structures. A reverse-biased diode may be connected to the signal line to protect a gate dielectric formed outside the DNW and is connected to the drain of the transistor formed inside the DNW.
    Type: Application
    Filed: March 28, 2012
    Publication date: October 3, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: David YEN, Sung-Chieh LIN, Kuoyuan (Peter) HSU
  • MEMORY ERROR CORRECTION
    Publication number: 20130262962
    Abstract: In a method, by a first circuit, a plurality of bits is converted in a first format to a second format. By a second circuit, the plurality of bits in the second format is used to program a plurality of memory cells corresponding to the plurality of bits. The first circuit and the second circuit are electrically coupled together in a first chip. The plurality of bits is selected from the group consisting of 1) address information, cell data information, and program information of a memory cell that has an error; and 2) word data information of a first word and error code and correction information corresponding to the word data information of the first word.
    Type: Application
    Filed: March 29, 2012
    Publication date: October 3, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yun-Han CHEN, Sung-Chieh LIN, Kuoyuan (Peter) HSU
  • Electrical fuse bit cell
    Patent number: 8542549
    Abstract: An electrical fuse (eFuse) bit cell includes a program transistor, a read transistor, and an eFuse. The program transistor has a first program terminal, a second program terminal, and a third program terminal. The read transistor has a first read terminal, a second read terminal, and a third read terminal. The eFuse has a first end and a second end. The first end, the first program terminal, and the second read terminal are coupled together. The read transistor is configured to be off and the program transistor is configured to be on when the eFuse bit cell is in a program mode. The program transistor is configured to be off and the read transistor is configured to be on when the eFuse bit cell is in a read mode.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: September 24, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Chieh Lin, Wei-Li Liao, Kuoyuan (Peter) Hsu
  • SIGNAL TRACKING IN WRITE OPERATIONS OF MEMORY CELLS
    Publication number: 20130242678
    Abstract: In a method, a first edge of a first tracking signal in a first direction of a memory array is generated. A first edge of a second tracking signal in a second direction of the memory array is generated. A first edge of a write-timing control signal is generated based on a slower edge of the first edge the first tracking signal and of the first edge of the second tracking signal. The first edge of the write-timing control signal is used to generate a second edge of the second tracking signal.
    Type: Application
    Filed: March 13, 2012
    Publication date: September 19, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bing WANG, Kuoyuan (Peter) HSU, Young Suk KIM