Patents by Inventor Peter Hsu
Peter Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130221995Abstract: An amplifying circuit comprises a bias circuit, a reference circuit, a first circuit, and an amplifying sub-circuit. The bias circuit is configured to provide a bias current. The reference circuit is configured to provide a first differential input based on a reference resistive device and a reference current derived from the bias current. The first circuit is configured to provide a second differential input based on a first current and a first resistance. The amplifying sub-circuit is configured to receive the first differential input and the second differential input and to generate a sense amplifying output indicative of a resistance relationship between the first resistance and a resistance of the reference resistive device.Type: ApplicationFiled: February 28, 2012Publication date: August 29, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Ming Hung, Sung-Chieh Lin, Kuoyuan (Peter) Hsu
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Publication number: 20130215693Abstract: A time delay is determined to cover a timing of a memory cell in a memory macro having a tracking circuit. Based on the time delay, a capacitance corresponding to the time delay is determined. A capacitor having the determined capacitance is utilized. The capacitor is coupled to a first data line of a tracking cell of the tracking circuit. A first transition of the first data line causes a first transition of a second data line of the memory cell.Type: ApplicationFiled: February 17, 2012Publication date: August 22, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Derek C. TAO, Young Seog KIM, Kuoyuan (Peter) HSU, Bing WANG, Annie-Li-Keow LUM
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Publication number: 20130208554Abstract: A tracking circuit in a memory macro includes a data line, a first tracking cell, and a plurality of transistors. The first tracking cell is electrically coupled to the data line. The plurality of transistors is electrically coupled to the data line. The plurality of transistors is configured to cause a delay on a transition of a signal of the data line based on a delay current. The signal of the data line is configured for use in generating a signal of a control line of a memory cell of the memory macro.Type: ApplicationFiled: February 15, 2012Publication date: August 15, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Bing WANG, Kuoyuan (Peter) HSU
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Patent number: 8482952Abstract: A one time programming (OTP) memory cell includes a first transistor and a second transistor. The first transistor has a first drain, a first source, a first gate, and a first normal operational voltage value higher that a second normal operational voltage value of the second transistor. The second transistor has a second drain, a second source, and a second gate. The first source is coupled to the second drain. The second source is configured to detect data stored in the OTP memory cell.Type: GrantFiled: February 17, 2011Date of Patent: July 9, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Chieh Lin, Wei-Li Liao, Kuoyuan (Peter) Hsu
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Publication number: 20130155799Abstract: A method of reading an eFuse in a column of eFuse memory cells includes electrically disconnecting a first end of the eFuse from a first electrical path. A second electrical path between a second end of the eFuse and a node is activated to bypass a third electrical path, where the third electrical path includes a diode device between the second end of the eFuse and the node. A footer coupled with the node is turned on.Type: ApplicationFiled: February 20, 2013Publication date: June 20, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sung-Chieh LIN, David YEN, Wei-Li LIAO, Jiann-Tseng HUANG, Kuoyuan (Peter) HSU
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Patent number: 8466732Abstract: An input of a first inverter is configured to serve as an input node. An output of the first inverter is coupled to an input of a second inverter. An output of the second inverter is configured to serve as an output node. An input of a third inverter is coupled to an input of the first inverter. A gate of a first NMOS transistor is coupled to an output of the third inverter. A drain of the first NMOS transistor is coupled to the second inverter. A source of the first NMOS transistor is configured to serve as a level input node. When the input node is configured to receive a low logic level, the output node is configured to receive a voltage level provided by a voltage level at the level input node.Type: GrantFiled: October 8, 2010Date of Patent: June 18, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Hung Chen, Kuoyuan (Peter) Hsu, David Yen, Sung-Chieh Lin
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Publication number: 20130148439Abstract: A memory circuit including at least one memory cell connected to a bit line. The memory circuit further includes a means for providing a bit line reference voltage VBLref to the bit line. A VBLref/VDD ratio of the bit line reference voltage VBLref to a power voltage VDD is adjustable corresponding to a change of the power voltage VDD, and the VBLref/VDD ratio ranges from about 0.4 to about 0.53.Type: ApplicationFiled: February 5, 2013Publication date: June 13, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Chieh HUANG, Kuoyuan (Peter) HSU
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Publication number: 20130126979Abstract: A method of forming an integrated circuit includes forming at least one transistor over a substrate. Forming the at least one transistor includes forming a gate dielectric structure over a substrate. A work-function metallic layer is formed over the gate dielectric structure. A conductive layer is formed over the work-function metallic layer. A source/drain (S/D) region is formed adjacent to each sidewall of the gate dielectric structure. At least one electrical fuse is formed over the substrate. Forming the at least one electrical fuse includes forming a first semiconductor layer over the substrate. A first silicide layer is formed on the first semiconductor layer.Type: ApplicationFiled: November 22, 2011Publication date: May 23, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chan-Hong CHERN, Fu-Lung HSUEH, Kuoyuan (Peter) HSU
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Publication number: 20130107603Abstract: A circuit includes a fuse circuit and a control circuit. The fuse circuit has an electrical fuse. The control circuit is configured to receive an input signal having an input pulse, and, based on a feedback signal from the fuse circuit, generates a read pulse smaller than the input pulse for use in reading the data stored in the electrical fuse.Type: ApplicationFiled: October 31, 2011Publication date: May 2, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jiann-Tseng HUANG, Sung-Chieh LIN, Kuoyuan (Peter) HSU
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Publication number: 20130100756Abstract: A mechanism of reconfiguring an eFuse memory array to have two or more neighboring eFuse bit cells placed side by and side and sharing a program bit line. By allowing two or more neighboring eFuse bit cells to share a program bit line, the length of the program bit line is shortened, which results in lower resistivity of the program bit line. The width of the program bit line may also be increased to further reduce the resisivity of program bit line. Program bit lines with low resistance and high current are needed for advanced eFuse memory arrays using low-resistivity eFuses.Type: ApplicationFiled: October 21, 2011Publication date: April 25, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Li LIAO, Sung-Chieh LIN, Kuoyuan (Peter) HSU
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Publication number: 20130088925Abstract: A semiconductor structure includes a first strap cell, a first read port, and a first VSS terminal. The first strap cell has a first strap cell VSS region. The first read port has a first read port VSS region, a first read port read bit line region, and a first read port poly region. The first VSS terminal is configured to electrically couple the first strap cell VSS region and the first read port VSS region.Type: ApplicationFiled: October 6, 2011Publication date: April 11, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jacklyn CHANG, Derek C. TAO, Yukit TANG, Kuoyuan (Peter) HSU
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Publication number: 20130088926Abstract: A tracking edge of a tracking signal is activated. A buffer is turned off and a latching circuit is turned on, based on the tracking edge of the tracking signal. A buffer output of the buffer is coupled to a latch output of the latching circuit at a node. The buffer receives a data line of a memory macro.Type: ApplicationFiled: October 5, 2011Publication date: April 11, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Derek C. TAO, Annie-Li-Keow LUM, Yukit TANG, Kuoyuan (Peter) HSU
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Patent number: 8411483Abstract: A one time programming (OTP) memory array is divided into a user section and a test section. The cells in the user section and in the test section are configured to form a checkerboard pattern, that is, having repeats of one user cell and one test cell in both column and row directions. Programming the test section and various additional tests are performed to both the user and test sections and other circuitry of the memory array while the user section is not programmed. Even though the OTP user section is not programmed or tested, the provided tests in accordance with embodiments of the invention can provide a very high probability that the OTP memory including the user section is of high quality, i.e., the OTP cells in the user section can be programmed and function appropriately.Type: GrantFiled: July 9, 2010Date of Patent: April 2, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Chieh Lin, Kuoyuan (Peter) Hsu
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Patent number: 8400860Abstract: Some embodiments regard a memory array that has a plurality of rows and columns. A column includes a program control device, a plurality of eFuse memory cells in the column, a sense amplifier, and a bit line coupling the program control device, the plurality of memory cells in the column, and the sense amplifier. A row includes a plurality of eFuse memory cells in the row, a word line coupling the plurality of eFuse memory cells in the row, and a footer configured as a current path for the plurality of eFuse memory cells in the row.Type: GrantFiled: July 20, 2010Date of Patent: March 19, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Chieh Lin, David Yen, Wei-Li Liao, Jiann-Tseng Huang, Kuoyuan (Peter) Hsu
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Patent number: 8391094Abstract: A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a bit line. The memory circuit includes a means for providing a bit line reference voltage VBLref to the bit line, wherein a VBLref/VDD ratio of the bit line reference voltage VBLref to a power voltage VDD is adjustable corresponding to a change of the power voltage VDD.Type: GrantFiled: January 22, 2010Date of Patent: March 5, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Chieh Huang, Kuoyuan Peter Hsu
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Publication number: 20130039117Abstract: An electrical fuse (eFuse) bit cell includes a program transistor, a read transistor, and an eFuse. The program transistor has a first program terminal, a second program terminal, and a third program terminal. The read transistor has a first read terminal, a second read terminal, and a third read terminal. The eFuse has a first end and a second end. The first end, the first program terminal, and the second read terminal are coupled together. The read transistor is configured to be off and the program transistor is configured to be on when the eFuse bit cell is in a program mode. The program transistor is configured to be off and the read transistor is configured to be on when the eFuse bit cell is in a read mode.Type: ApplicationFiled: August 8, 2011Publication date: February 14, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sung-Chieh LIN, Wei-Li LIAO, Kuoyuan (Peter) HSU
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Publication number: 20130038375Abstract: A circuit includes a power switch and a level shifter. The level shifter has a node and an assistant circuit. The node is configured to control the power switch. The assistant circuitry is coupled to the node and configured for the node to receive a first voltage value through the assistant circuit. The first voltage value is different from a second voltage value of an input signal received by the level shifter.Type: ApplicationFiled: August 8, 2011Publication date: February 14, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sung-Chieh LIN, Wei-Li LIAO, Kuoyuan (Peter) HSU
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Patent number: 8339890Abstract: A circuit with leakage and data retention control includes at least one memory cell in a first memory array. The at least one memory cell is coupled to a first power supply voltage and a virtual ground. The circuit includes a current source and an NMOS transistor. The drain of the NMOS transistor is coupled to the virtual ground and the gate of the NMOS transistor is coupled to the current source.Type: GrantFiled: May 27, 2010Date of Patent: December 25, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuoyuan (Peter) Hsu, Yukit Tang, Jacklyn Chang
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Publication number: 20120320700Abstract: This description relates to a circuit including a bit line. The circuit further includes at least one memory bank. The at least one memory bank includes at least one memory cell, a first device configured to provide a current path between the bit line and the at least one memory cell when the at least one memory cell is activated, and a second device configured to reduce current leakage between the bit line and the at least one memory cell when the at least one memory cell is deactivated. The circuit further includes a tracking device configured to receive a minor current substantially equal to a current along the current path, the tracking device configured to have a resistance substantially equal to a cumulative resistance of all memory cells of the at least one memory cell.Type: ApplicationFiled: August 27, 2012Publication date: December 20, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sung-Chieh LIN, Kuoyuan (Peter) HSU, Jiann-Tseng HUANG, Wei-Li LIAO
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Patent number: 8305827Abstract: A memory array comprises a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns includes a first power supply node configured to provide a first voltage, a second power supply node configured to provide a second voltage, and a plurality of internal supply nodes electrically coupled together and configured to receive the first voltage or the second voltage for a plurality of memory cells in the column and a plurality of internal ground nodes. The internal ground nodes are electrically coupled together and configured to provide at least two current paths for the plurality of memory cells in the column.Type: GrantFiled: July 13, 2010Date of Patent: November 6, 2012Inventors: Derek C. Tao, Kuoyuan (Peter) Hsu, Dong Sik Jeong, Young Suk Kim, Young Seog Kim, Yukit Tang