Abstract: Among various embodiments of the present disclosure, displaying electrophoretic particles can be performed by configuring an electrophoretic display for directed spreading of electrophoretic particles across a number of substantially planar display electrodes. Such a configuration can be accomplished by controlling planar spreading of the electrophoretic particles in an electrophoretic pixel with an electrical field between an in-plane storage electrode and an in-plane activation electrode. The in-plane activation electrode can be connected to an in-plane display electrode, which extends across a first area in the electrophoretic pixel adjacent to a display aperture having a second area that is substantially coextensive with the first area.

Abstract: An electrophoretic display apparatus includes an array of cells each comprising first and second electrodes and a plurality of electrophoretic particles disposed between the electrodes, wherein the particles are dispersed in a host fluid and are multistable in positions between the electrodes; and drive circuitry in electrical communication with each of the electrodes. The drive electronics are configured to transition addressed cells of the array from a first optical state to a second optical state with a plurality of successive write signals.

Abstract: Embodiments 1of an apparatus with first and second display panels and a resistor multiplexer are disclosed.

Abstract: Embodiments of sensing light are disclosed.

Abstract: A method and apparatus apply an electric field across active layer, wherein active layer is configured to change from a first light attenuating state to a second lesser light attenuating state in response to the applied the electric field and wherein the second lesser light attenuating state permits light to be reflected from a light reflective face.

Abstract: Embodiments including a charge responsive optical material are disclosed.

Abstract: A semiconductor substrate is provided over which electrically conductive columns are formed along with electrically conductive rows crossing over the electrically conductive columns. A plurality of memory components are formed each having a resistance value corresponding to multiple logical bits and non-volatile memory cells are each formed by connecting a memory component between an electrically conductive row and an electrically conductive column.

Abstract: A memory system, including a first electrode, a memory storage element, and a control element. The control element having a breakdown voltage. The breakdown voltage is increased by partially-processing the control element. In one aspect, the partial-processing results by processing the control element for a briefer duration than the memory storage element. In another aspect, the partial-processing results by forming the control element from a plurality of layers, some of the plurality of layers are unprocessed while other ones of the plurality of layers are fully processed.

Abstract: A memory system, including a first electrode, a memory storage element, and a control element. The control element having a breakdown voltage. The breakdown voltage is increased by partially-processing the control element. In one aspect, the partial-processing results by processing the control element for a briefer duration than the memory storage element. In another aspect, the partial-processing results by forming the control element from a plurality of layers, some of the plurality of layers are unprocessed while other ones of the plurality of layers are fully processed.

Abstract: Systems and methods for storing data are provided. A representative system for storing data includes a magnetic random access memory (MRAM) device having a plurality of memory cells. Each memory cell includes a magnetic tunnel junction and a non-magnetic tunnel junction that are connected in series. The magnetic tunnel junction stores a bit value corresponding to a logic high (1) or a logic low (0). The non-magnetic tunnel junction provides little resistance when the memory cell is being read, and a substantially high resistance when the memory cell is not being read. As a result, a negligible level of parasitic current leaks through memory cells that are not being read.

Abstract: A magnetic memory cell made on a substrate has a first metal conductor, a first magnetic layer disposed on the first metal conductor, a planar interlayer dielectric (ILD) having a via opening extending through it to the first magnetic layer, a buried tunnel junction over the first magnetic layer within the via opening, a second magnetic layer filling the via opening and burying the tunnel junction, and a second metal conductor coupled to the second magnetic layer. Methods for using the memory cell in memories and other devices and methods specially adapted for fabrication of the memory cell are disclosed.

Abstract: A non-volatile memory cell of the type having a control element and a storage element has a storage element including a first material characterized by having a phase change in a predetermined temperature range, a second material having a negative differential resistance characteristic, the second material being in contact with the first material and being electrically coupled to the control element. The control element is operated to induce filamentary conduction through the second material such that the filamentary conduction causes the temperature of at least a portion of the first material to reach the predetermined temperature range, whereby a phase change occurs in at least a portion of the first material.

Abstract: A magnetic memory cell made on a substrate has a first metal conductor, a first magnetic layer disposed on the first metal conductor, a planar interlayer dielectric (ILD) having a via opening extending through it to the first magnetic layer, a buried tunnel junction over the first magnetic layer within the via opening, a second magnetic layer filling the via opening and burying the tunnel junction, and a second metal conductor coupled to the second magnetic layer. Methods for using the memory cell in memories and other devices and methods specially adapted for fabrication of the memory cell are disclosed.

Abstract: Interconnection structures for integrated circuits have a first array of cells, at least a second array of cells parallel to the first array, and interconnections disposed for connecting cells of the first array with cells of the second array, at least some of the interconnections being disposed along axes oriented obliquely to the first and second arrays. First and second sets of oblique axes of interconnections may be parallel or opposed to each other. The interconnections may include obliquely slanted pillars or stair-stepped pillars disposed along the oblique axes. Methods for fabricating and using such structures are disclosed.

Abstract: An array of MEMS devices having column lines and row lines, such as a light modulator array, is controlled in response to an input signal by providing a number of discrete voltages, multiplexing from the discrete voltages a selected voltage to be applied to each MEMS device of the array, and enabling application of the selected discrete voltage to each MEMS device of the array.

Abstract: A semiconductor substrate is provided over which electrically conductive columns are formed along with electrically conductive rows crossing over the electrically conductive columns. A plurality of memory components are formed each having a resistance value corresponding to multiple logical bits and non-volatile memory cells are each formed by connecting a memory component between an electrically conductive row and an electrically conductive column.

Abstract: Systems and methods for storing data are provided. A representative system for storing data includes a magnetic random access memory (MRAM) device having a plurality of memory cells. Each memory cell includes a magnetic tunnel junction and a non-magnetic tunnel junction that are connected in series. The magnetic tunnel junction stores a bit value corresponding to a logic high (1) or a logic low (0). The non-magnetic tunnel junction provides little resistance when the memory cell is being read, and a substantially high resistance when the memory cell is not being read. As a result, a negligible level of parasitic current leaks through memory cells that are not being read.

Abstract: A read-only memory device has multiple layers, where a first layer is formed on a semiconductor substrate, and one or more additional layers are formed over the first layer. Each layer has multiple non-volatile memory cells that include a memory component connected between electrically conductive traces. A memory component indicates a resistance value when a potential is applied to a selected memory cell. A memory component can be formed with a resistor, a resistor in series with a control element, or an anti-fuse device in series with a diode. A memory device having memory components that include an anti-fuse device can be programmed after manufacture, where an anti-fuse device indicates a high resistance value corresponding to a logical one when the memory device is manufactured, and indicates a low resistance value corresponding to a logical zero when a junction of the anti-fuse device is penetrated to form an electrical connection.

Abstract: A read-only memory device is described having non-volatile memory cells that include a memory component connected between electrically conductive traces. A memory component is formed to include a resistor that indicates a resistance value when a potential is applied to a selected memory cell. The resistance value of a memory component in an individual memory cell corresponds to multiple logical bits. The resistance value of a memory component corresponding to a set of logical bits can be based on a thickness and/or an area of electrically resistive material that forms the memory component, and/or based on the geometric shape of the memory component, where different geometric shapes of the electrically resistive material have different resistance values that correspond to different sets of logical bits.

Abstract: Methods for storing a bit sequence are provided. A representative method for storing a bit sequence includes converting a first bit sequence containing a first number of low-resistance bits into a second bit sequence containing a second number of low-resistance bits that is lower than the first number of low-resistance bits, and then storing the second bit sequence in a resistance-based memory device. Systems, computer-readable media, and other methods for storing and retrieving a bit sequence are also provided.