Abstract: A method and apparatus for computing flush masks in a multi-threaded processing system provides fast and low-logic-overhead computation of a flush result in response to multiple flush request sources. A flush mask register file is implemented by multiple cells in an array where cells are absent from the diagonal where the column index is equal to the row index. Each cell has a vertical write enable and a horizontal write enable. When a row is written to validate that row's tag value, the is column having an index equal to the row selector is automatically reset (excepting the bit corresponding to the absent cell mentioned above). On a read of a row in the array, a wired-AND circuit provided at each column provides a bit field corresponding to other rows that have been written since a last reset of the row, which is a flush mask indicating newer tags and the selected tag.

Abstract: According to one form of the invention, an apparatus includes first timing circuitry, at least one stage of logic circuitry and second timing circuitry. The first timing circuitry has a first data input and a latch with a latch data input coupled to the first data input and a latch data output coupled to an input of the least one stage of logic circuitry. The second timing circuitry has a latch and an edge detector with respective latch and edge detector data inputs coupled to a data output of the at least one stage of logic circuitry. The edge detector has an output coupled to a control input of the second timing circuitry latch for triggering capture of an output data signal on the data output of the at least one stage of logic circuitry responsive to detecting a signal transition.

Abstract: According to one form of the invention, an apparatus includes first timing circuitry, at least one stage of logic circuitry and second timing circuitry. The first timing circuitry has a first data input and a latch with a latch data input coupled to the first data input and a latch data output coupled to an input of the least one stage of logic circuitry. The second timing circuitry has a latch and an edge detector with respective latch and edge detector data inputs coupled to a data output of the at least one stage of logic circuitry. The edge detector has an output coupled to a control input of the second timing circuitry latch for triggering capture of an output data signal on the data output of the at least one stage of logic circuitry responsive to detecting a signal transition.

Abstract: A method and apparatus for reducing power dissipation within a functional unit of a microprocessor includes a power sensing circuit for sensing power dissipation of the functional unit. A low power mode identifying circuit identifies when the measured power dissipation of the functional unit exceeds a predetermined amount or value. Upon such a condition, a low power mode circuit operates the functional unit in a low power mode thereby reducing its power dissipation. Operation of the functional unit in the low power mode continues until the power dissipation reaches a safe level. The functional unit internally determines power dissipation and selectively enters a low power mode to reduce power dissipation of the functional unit. Low power mode operation of the functional unit reduces power dissipation of the functional unit.

Abstract: A method and memory array for reducing sub-threshold leakage in a memory array. A memory array may include a plurality of rows where each row may include one or more groups of cells. Within each group of cells, each cell may be coupled to a ground path and to a power path. A device, e.g., n-type transistor, p-type transistor, may be coupled to either the ground or power path in each group of cells thereby permitting the passing of the sub-threshold leakage from those cells in that group through the device. Consequently, the sub-threshold leakage in the memory array may be reduced.

Abstract: The invention relates to an agent for treating skin diseases and/or functional disorders of the skin on the basis of different medicaments and/or auxiliary substances through promotion of penetration from topical formulations into the skin. According to the invention, the agent is composed of a hyaluronate lyase produced by microbial means and a medicament, preferably a hydrophilic medicament and/or auxiliary substances in different galenic formulations including colloidal carrier systems. The areas of application for the invention in human and veterinary medicament relate to the treatment, prophylaxis and/or metaphylaxis of skin diseases, functional disorders of the skin, the processes of skin ageing and dry skin conditions.

Abstract: Rheumatoid arthritis is a chronic inflammatory disease, leading to joint destruction. Conventional therapy is based on pain-reduction and an improvement in the frictional properties of joints, in order to delay the time for operative intervention. A lack of specifically-acting agents for drug-based therapy for arthritis exists. The formulations comprise sulphated hyaluronic acids with varying degrees of sulphation, or the pharmacologically acceptable salts thereof and, optionally, hyaluronic acid and/or hyaluronic acid uronide. The pharmaceutical formulations are highly concentrated injection preparations with an aqueous, viscous, gel-like, or paste-like form, or a low-concentration rinsing fluid for intra-articular application.

Abstract: A register for a computer processor removes the parity check from the critical path of CPU operation, and delays the parity check to the next immediate clock cycle. The register has a memory array, and read and write decoders for accessing the memory array using select lines. The select lines are also connected to read and write address latches which are used to index a parity bit array. When a value is written to, or read from, the memory array, its corresponding parity bit is calculated and either stored in the parity bit array (for a write operation), or compared to an existing parity bit array entry (for a read operation). The parity check is performed on a copy of the value contained in a read data latch or a write data latch. Each data latch has an input connected to a respective read or write port of the memory array. The latches delay the parity check by only one cycle.

Abstract: The invention relates to an agent for the treatment, prophylaxis and metaphylaxis of functional and structural disorders of the skin caused by external factors. The agent contains a hyaluronic acid partially digested with a microbiological hyaluronate lyase. The hyaluronic acid fragment mixture is incorporated in different galenic formulations to which other hydrophilic and/or lipophilic active substances and/or auxiliary substances can be added. Fields of application of the invention in human and veterinary medicine relate to the treatment and/or the prophylaxis of skin damage caused by environmental factors including UV, dry skin conditions and skin ageing.

Abstract: A method and apparatus is provided for enabling a static timing tool to analyze and test register files in integrated circuits to find correct paths and ignore detected contention. This is achieved by utilizing pattern matching in the static timing tool and having the tool perform certain operations on the transistors of the pattern matched. The methodology includes considering the write word lines as clock nodes, disabling signal propagation through the memory element components, forcing predetermined internal nodes to be of inverse polarity, establishing signal direction through the circuit elements, and indicating that one or more of the predetermined nodes are not to be reported.

Abstract: A system, method, and computer program product are disclosed for automatically performing timing checks on a memory cell. A static timing tool is provided that includes multiple, different standard timing elements. Each standard timing element is associated with one or more standard timing checks. The memory cell is represented using one or more of the standard timing elements. Standard timing checks associated with the timing elements used to represent the memory cell are used to verify timing in the memory cell.

Abstract: A noise suppression circuit for suppressing above-ground noise is disclosed. The noise suppression circuit for suppressing noises includes a first inverter, a second inverter, and a one-shot circuit. The first inverter, connected to an input line, switches at a first voltage value above which a noise-coupling event is suspected. The second inverter, also connected to the input line, switches at a second voltage value above which a full-switch input is assumed. A first transistor is coupled to the input line. A second transistor passes an output of the second inverter to a gate of the first transistor when an output of the one-shot circuit is high. The third transistor holds the gate of the first transistor low when the output of the one-shot circuit is low.

Abstract: A system, method, and computer program product are disclosed for automatically performing timing checks on a memory cell. A static timing tool is provided that includes multiple, different standard timing elements. Each standard timing element is associated with one or more standard timing checks. The memory cell is represented using one or more of the standard timing elements. Standard timing checks associated with the timing elements used to represent the memory cell are used to verify timing in the memory cell.

Abstract: A Self-Timed CMOS Static Circuit Technique has been invented that provides full handshaking to the source circuits; prevention of input data loss by virtue off interlocking both internal and incoming signals; full handshaking between the circuit and sink self-timed circuitry; prevention of lost access operation information by virtue of an internal lock-out for the output data information; and plug-in compatibility for some classes of dynamic self-timed systems. The net result of the overall system is that static CMOS circuits can now be used to generate a self-timed system. This is in contrast to existing self-timed systems that rely on dynamic circuits. Thus, the qualities of the static circuitry can be preserved and utilized to their fullest advantage.

Abstract: A system within a complementary logic circuit having a true tree and a complement tree, for correcting an illegal non-complementary output caused by a defect in either tree. A complementary logic circuit has a true tree for producing a true signal and a complement tree for producing a complement signal. The true signal is utilized to generate a true output signal from the complementary logic circuit and the complement signal is utilized to generate a complement output signal from the complementary logic circuit. Multiplexing means within the true and complement trees are utilized to selectively replace the true (complement) signal with the complement (true) signal within the true (complement) tree, such that the complement (true) tree is utilized to correct the occurrence of a proscribed non-complementary condition at the output of the complementary logic circuit to diagnose a defect during diagnostic testing or to override a defect during normal runtime operation.

Abstract: A system and method for detecting and rectifying a proscribed non-complementary output from a complementary logic circuit. A complementary logic circuit having a true tree and a complement tree is provided. The true tree produces a true signal utilized to generate a true output signal from the complementary logic circuit. The complement tree produces a complement signal utilized to generate a complement output signal from the complementary logic circuit. Logic means coupled to the output of the complementary logic circuit detect an occurrence of a non-complementary output from the complementary logic circuit. Multiplexing means within the true tree is utilized to selectively replace the true signal with the complement signal within the true tree in response to detection by the logic means of a non-complementary output, such that a non-complementary output is seamlessly detected and rectified.

Abstract: A non-conventional CAM (content addressable memory) and register mapper organization and circuit implementation is provided which allows simultaneous execution of a large number of CAM searches. All compare circuits are placed outside of the CAM in separate match arrays where the actual comparisons occur. The CAM cell contains only latches to hold the CAM stored bit of data and a multi-port MUX to update the CAM content. The CAM bits are driven to the match arrays for match generation. The structure of the CAM and search engine facilitates implementation of the register mapper as a group of custom arrays. Each array is dedicated to execute a specific function. All of the arrays are aligned and each row of an array is devoted to one register to keep current state, shadow state and controls for that register. In an exemplary embodiment, eight custom arrays are used to execute various functions of the register mapper.

Abstract: An aluminum-based alloy having the following composition, % w/w: Lithium 1.5-1.9 Magnesium 4.1-6.0 Zinc 0.1-1.5 Zirconium 0.05-0.3  Manganese 0.01-0.8  Hydrogen 0.9 × 10−5-4.5 × 10−5 and at least one element selected from the following group: Beryllium 0.001-0.2  Yttrium 0.01-0.5 Scandium 0.01-0.3 Aluminum Remainder The process of heat treating the alloy includes the steps of quenching the alloy from a temperature of 400-500° C. in cold water or air, stretched-adjusting it to increase ductility up to 0 2 %, and a three stage heat treatment, in which in stage 1 the alloy is heated at 80-90° C. over the course of 3-12 h, in stage 2 it is heated at 110-185° C. over the course of 10-58 h, and in stage 3 it is heated at 90-110° C. for 14 h, or at a cooling rate of 2-8° C. C/h.

Abstract: A master-slave flip-flop circuit (200, 200′) includes a master latch circuit (202) and slave latch circuit (203). A hold control component (220) included in the master latch circuit (202) is interposed between a master latch node (ML) and a slave input node (SI). The hold control component blocks the transfer of data from the master latch node (ML) to the slave input node (SI) in response to a hold input. In the preferred form of the invention of the hold control component (220) comprises a tri-state inverter having an input connected to the master latch node (ML) and an output connected to the slave input node (SI). The hold input, comprising a high level hold signal and its complementary or inverted signal, disables the tri-state inverter and thus prevent data from being transferred from the master latch node (ML) to the slave input node (SI).

Abstract: A wafer design layout and method of producing multiple integrated chip types using a single set of masks for a wafer and then at the time the type of chip desired is known, using a few customizing steps to produce the final integrated chip is provided. In one embodiment, the wafer layout includes a plurality of groupings of components and a plurality of dicing channels separating each of the components from others of the components. After the particular type of integrated circuit chip desired is selected, the wafer may then have the final few layers processed and the chips removed using the appropriate dicing channels for the integrated circuit chip desired.