Abstract: An aluminum-based alloy having the following composition, % w/w: Lithium 1.5-1.9 Magnesium 4.1-6.0 Zinc 0.1-1.5 Zirconium 0.05-0.3 Manganese 0.01-0.8 Hydrogen 0.9 × 10−5-4.5 × 10−5 and at least one element selected from the following group: Beryllium 0.001-0.2 Yttrium 0.01-0.5 Scandium 0.01-0.3, Aluminum Remainder The process of heat treating the alloy includes the steps of quenching the alloy from a temperature of 400-500° C. in cold water or air, stretched-adjusting it to increase ductility up to 0 2 %, and a three stage heat treatment, in which in stage 1 the alloy is heated at 80-90° C. over the course of 3-12 h, in stage 2 it is heated at 110-185° C. over the course of 10-58 h, and in stage 3 it is heated at 90-110° C. for 14 h, or at a cooling rate of 2-80° C. C/h.

Abstract: Dynamic logic circuits with reduced evaluation time provide faster output in dynamically evaluating logic circuits by increasing the rate of change of the voltage at the junction of logic input ladders. The circuits use a cross-coupled amplifier to charge the input ladder combining node once the node begins to evaluate.

Abstract: A circuit evaluates a plurality of data inputs, provides for stabilization of the evaluation, and then drives the evaluation from the circuit. The providing of the stabilization is performed by delaying an activation signal, which controls the evaluation circuitry. The activation signal may be either a clock signal or a reset signal. This circuit may be an address decoder that decodes certain ones of the address signals during the evaluation phase, and then drives the evaluation during the second phase.

Abstract: A method and system for detecting faults within dual-rail complementary logic circuits. A method and system are disclosed for detecting faults within dual-rail complementary logic circuits. A dual-rail complementary logic circuit is coupled to an associated complementary fault detection circuit within an integrated circuit. Thereafter, the presence of a non-complementary logic signal can be detected at an output of the complementary fault detection circuit, in response to providing an input signal at an input of the dual-rail complementary logic circuit, such that the presence of a non-complementary logic signal at an output of the complementary fault detection circuit indicates the presence of a fault within the associated complementary logic circuit.

Abstract: A noise suppression circuit for suppressing noises above and below reference voltages is provided. The noise suppression circuit for suppressing noises includes a clamping transistor, a feedback circuit, and a presetting means for presetting an internal latch of the noise suppression circuit to a predetermined state. The predetermined state is a high state or a low state depending upon the type of noise suppression accomplished by the circuit. After the occurrence of a noise coupling event, the clamping transistor restores the state of a data input of a circuit to which the suppression circuit is providing protection. The feedback circuit then turns off the clamping transistor after a predetermined amount of time.

Abstract: For transmitting information on a plurality of integrated circuit conductive lines, n conductive lines are provided on a path in an integrated circuit. The path has first and second portions, and an interposing, transition portion. The lines have first positions with respect to one another in the first portion, and certain of the lines change relative positions in the transition portion, so that the lines have second positions with respect to one another in the second portion. The information is encoded in a format wherein no more than one of the n lines has a signal asserted thereon at a time, so that there is a reduction in noise induced among the lines.

Abstract: A circuit evaluates a plurality of data inputs, provides for stabilization of the evaluation, and then drives the evaluation from the circuit. The providing of the stabilization is performed by delaying an activation signal, which controls the evaluation circuitry. The activation signal may be either a clock signal or a reset signal. This circuit may be an address decoder that decodes certain ones of the address signals during the evaluation phase, and then drives the evaluation during the second phase.

Abstract: False transitions resulting from capacitive coupling between parallel interconnects driven by dynamic circuits are reduced by classifying interconnects based on the timing of expected data transitions in the signals they carry. Interconnects carrying signals expected to transition during a first portion of a processor cycle are treated as one category, while interconnects carrying signals expected to transition during a second, different portion of the processors cycle are treated as a second category. Interconnects of different categories are interdigitated, a resets of dynamic driving circuits are tuned so that, at any given time, alternate interconnects are “quiet” or stable. Therefore interconnects being driven with data transitions are directly adjacent to quiet lines, and foot devices are implemented as necessary to prevent coupling expected during the reset phase.

Abstract: A noise suppression circuit for suppressing noises above and below reference voltages is disclosed. The noise suppression circuit for suppressing noises includes a means for generating a power-on-reset signal, a clamping transistor, and a feedback circuit. The means for generating a power-on-reset signal presets an internal latch of the noise suppression circuit to a predetermined state, such as a logical high state. The clamping transistor restores the state of a data input of a circuit to which the noise suppression circuit is providing protection, after the occurrence of a noise coupling event. The feedback circuit then turns off the clamping transistor after a predetermined amount of time.

Abstract: A domino logic circuit having output noise elimination is disclosed. A compound domino logic circuit includes at least two trees of logic devices arranged in parallel, with each tree having a precharge transistor connected to a power supply, and one or more input transistors coupled between the precharge transistor and ground. The precharge transistor receives a clock input while each of the one or more input transistors receives a signal input. The compound domino logic circuit also includes a logic gate coupled to the precharge transistor to produce a signal output. The logic gate includes at least two transistors connected in series. Further, an adjustment transistor is coupled to a node between the two transistors to ground.

Abstract: The present invention addresses the foregoing needs by providing a circuit implemented in SOI (silicon on insulator) CMOS, which includes a first node precharged to an activated level, a first transistor coupled between the first node and the second node, a second transistor coupled between the second node and a ground potential, and a third transistor coupled to the second node and operable for preventing the second node from rising to the activated level. The third transistor prevents the parasitic bipolar effect from raising this second node to the activated level. Essentially, the third transistor maintains the second node substantially at a ground level.

Abstract: An apparatus and method for controlling the power consumption of a logic device are implemented. The power dissipation, and consequently, the speed of a complementary metal oxide semiconductor (CMOS) logic device is substantially proportional to the speed of the device. The temperature of the logic device is controlled by controlling the device speed by adjusting the threshold voltage of the metal oxide semiconductor (MOS) devices forming the logic device under control. The threshold voltage of the devices is controlled by applying a back bias voltage between the bulk material in which each device under control is fabricated, and the most positive electrode of the device. The back bias voltage value is regulated in response to the logic device temperature, thereby closing a feedback loop.

Abstract: The present invention provides a method and system for providing observability of memory address access for self-timed cache designs. A system according to the present invention for determining which memory location has been accessed in a self-timed cache comprises a content addressable memory; a secondary memory coupled to the content addressable memory, wherein the secondary memory includes at least one memory location which may be selected by the content addressable memory based upon a self-timed cache access. The system further includes a test circuitry coupled to the content addressable memory, wherein the test circuitry stores a pointer which points to a selected memory location in response to the self-timed cache access of the secondary memory.

Abstract: A circuit evaluates a plurality of data inputs, provides for stabilization of the evaluation, and then drives the evaluation from the circuit. The providing of the stabilization is performed by delaying an activation signal, which controls the evaluation circuitry. The activation signal may be either a clock signal or a reset signal. This circuit may be an address decoder that decodes certain ones of the address signals during the evaluation phase, and then drives the evaluation during the second phase.

Abstract: A method and apparatus is provided for logical steering of instructions or operations to avoid power related hot spots on a microprocessor. The instructions are distributed to one of multiple units located within different areas of the integrated circuit. Each of the multiple functional units are identical or perform substantially the same function in response to the instruction. Power dissipation is measured within each of the areas in which a functionally equivalent unit is located. If the power dissipation within an area exceeds a predetermined amount or value, a localized heating problem exists within the area. The instruction is dispatched or routed to one of the other functional units located within an area not experiencing a localized heating problem, thus reducing the possibility of catastrophic failure due to overheating, decreasing overall chip power dissipation, increasing chip reliability, and increasing throughput.

Abstract: Logic circuitry added to each stage of a pipeline of staged logic circuitry sequentially removes a clock signal from each stage when data incoming to the pipeline is invalid, or not to be processed for any practical use. The same logic circuitry is also useful for reapplying the clock signal to the successive stages of the pipeline when valid data is to be processed by the pipeline.

Abstract: The invention relates to a processor having a data flow unit for processing data in a plurality of steps. In one version, the data flow unit includes a plurality of consecutive stages which include logic for performing steps of the data processing, the stages being coupled together by a data path, at least one stage being coupled to a transceiver which causes data to be provided to the stage for processing or to bypass the stage unprocessed in response to a stage enable signal; a synchronizer which receives processed data from the stages and causes the processed data to be provided to external logic in synchronization with a clock signal.

Abstract: From a first circuit, information is output in response to acknowledgement signals. From a second circuit, the acknowledgement signals are output in response to the second circuit receiving portions of the information from the first circuit. The portions and the acknowledgement signals are output asynchronously with respect to one another. With at least one of the first and second circuits, a signal having a logic state is received, the logic state is latched, and an operation is performed in response to the latched logic state.

Abstract: An apparatus to remove from operation a decoupling capacitor connected to a power supply providing power to logic circuitry in an integrated circuit. One technique for doing so is to connect a fuse in series with a decoupling capacitor. The present invention amplifies current transmitting through the fuse in a positive feedback manner to force the fuse to blow sooner than would normally occur. Therefore, when the current through the decoupling capacitor is deemed unacceptable, the fuse current is increased until such a time that the fuse opens.

Abstract: From a first circuit, first information is output in response to acknowledgement signals. From a second circuit, second information and the acknowledgement signals are output. The second information and the acknowledgement signals are output in response to the second circuit receiving portions of the first information from the first circuit during a functional mode of operation. The portions and the acknowledgement signals are output asynchronously with respect to one another. From a third circuit, third information is output in response to the second information. From a test circuit, the second information output from the second circuit is specified, so that the third circuit outputs the third information in response to the specified second information independent of the first information output from the first circuit during a test mode of operation.