Abstract: A method and apparatus for timing self-timed circuitry measures the cycle time of a self-timed system or circuit. An input pattern generator generates a plurality of data input patterns that are sequentially input to the self-timed system or circuit. A valid output signal, generated after the self-timed system or circuit produces output signal(s) in response to each data input pattern and signals the input pattern generator to change the input to the next data input pattern. A timer measures the total amount of time required for the self-timed system or circuit to generate output signal(s) in response to the sequential input of each of the data input patterns. A counter counts the number of times a valid output signal is generated as the apparatus loops through each of the data input patterns. The timer result is divided by the counter result to determine the average cycle time (time delay) of a self-timed system or circuit across multiple data input patterns.

Abstract: A system and method are provided which automatically change the output of an oscillator clock prior to its input to dynamic logic circuit elements as a system clock signal. The oscillator clock signal is controlled based upon a signal generated by a sensor which determines the power consumption of the integrated circuit. The frequency of the clocked signal is reduced (or increased) incrementally based upon the output of the sensor which detects the level of a specific circuit characteristic, relating to electrical power consumption. A pattern generator is used to input a digital signal to a series of interconnected registers which make up a loadable shift register. The output of the pattern generator is based upon the input from the sensor. The bits shifted through the shift register are ANDed with the oscillator clock signal to control the frequency of the system clock.

Abstract: The invention is disclosed as embodied in a data processing system circuit for outputting a signal based on an evaluation of input signals coupled to the circuit. The circuit has a number of transistors configured so that the output signal is triggered by a triggering combination of input signals. The circuit also has a discharge transistor coupled to a signal for switching the discharge transistor to a state tending to discharge a node in the circuit. The node must be discharged to a certain level to trigger the output signal, so that discharging the node after it has become charged up above the certain level tends to reduce evaluation time for the circuit.

Abstract: Logic circuitry implemented in a pipeline manner receives a request signal along with received data into the pipeline and proceeds to insure that each successive stage within the pipeline is placed into a standby state and out of a precharge state previous to the arrival of the data wave into each of the successive stages. The circuitry also resets each of the stages after a stage has evaluated the data. The logic circuitry may be employed within a multiplier array in a processor.

Abstract: A system and method are provided which automatically change the rate of data transfer between stages of control logic connected in a pipelined fashion, based upon a control signal generated by a sensor which determines the power consumption of the integrated circuit. Delay circuits are disposed intermediate of each stage in the pipeline and receive an input from the sensor which is connected to the delay circuits. The data input to the next subsequent stage from the previous stage in the pipeline is gated based on the state of the delay circuitry. That is, when the sensor determines that a high power condition exists, the delay circuitry is enabled such that the data transfer between stages in the pipeline slows down. However, when the sensor determines that the power consumption situation is at an acceptable level, the delay circuitry is disabled such that data can then be transferred between stages in the pipeline at a high frequency.

Abstract: A data processing apparatus has a number of data processors connected in a series by data lines so that data signals are processed in a preceding processor and communicated to a succeeding processor in the series. The apparatus has a number of control elements, where a control element has first and second inputs receiving processor status signals and an output sending a signal to enable processing. The control element output assumes a certain output state only if both inputs assume the state. The output, having assumed the state, holds the state, despite one of the inputs not holding the state, only if a certain one of the inputs does hold the state.

Abstract: A self-timed control circuit for self-resetting CMOS logic circuitry provides handshaking between macros to ensure that all data inputted to a particular macro is maintained by the source macros until all data inputs have been received. A data output signal from a macro is maintained until the macro receives a complete signal from all receiving macros indicating that the receiving macros have received all data inputs supplied to them.

Abstract: An electronic system for controlling the fuel injection of an internal-combustion engine based on the load, rotational speed, and temperature, as well as at least an oxygen probe reading in the exhaust pipe. The system determines basic injection-quantity signal as well as a transition-compensation signal to adapt the injection fuel quantity in situations of acceleration and deceleration. The system stores an engine characteristics map for a wall-film-quantity signal, and dividing factors for acceleration and deceleration. The system generates a correction value (Wkor) for the wall-film quantity signal and correction factors (FWS1kor, FWS2kor) for the two dividing factors. Three methods are provided for changing the correction factors in connection with the adaptation and these are based on a direct calculation, based on an estimation of the missing quantity and incremental calculation, and based on an incremental adjustment based on the evaluation of the oxygen-probe voltage.