Patents by Inventor Peter Johnson

Peter Johnson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130174117
    Abstract: System and method for forming a cloud appliance. The system includes a management server, an artifact repository, a continuous integration server, and build managers. The management server includes source code and a project script for forming the cloud appliance. The artifact repository stores artifacts required to build the cloud appliance and artifacts that comprise the built cloud appliance. The continuous integration server manages a build process, unit test process, and deployment process based on the project script. The build managers build the source code for customizing the virtual machine and store the built source code as the second artifacts in the artifact repository. The continuous integration server instantiates the virtual machine from template and customizes the virtual machine to form a customized virtual machine using the artifacts specified in the project script, a customization process for each of the artifacts based on a type of the artifact.
    Type: Application
    Filed: December 29, 2011
    Publication date: July 4, 2013
    Inventors: Christina Watters, Peter Johnson, Robert S. Baker
  • Publication number: 20130140654
    Abstract: A capacitive micromachined ultrasonic transducer (CMUT), which has a conductive structure that can vibrate over a cavity, has a number of vent holes that are formed in the bottom surface of the cavity. The vent holes eliminate the deflection of the CMUT membrane due to atmospheric pressure which, in turn, allows the CMUT to receive and transmit low frequency ultrasonic waves.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 6, 2013
    Inventors: Steven Adler, Peter Johnson, Ira Oaktree Wygant
  • Publication number: 20130140704
    Abstract: A capacitive micromachined ultrasonic transducer (CMUT), which has a conductive structure that can vibrate over a cavity, utilizes a thick oxide layer to substantially increase the volume of the cavity which, in turn, allows the CMUT to receive and transmit low frequency ultrasonic waves. In addition, the CMUT can include a back side bond pad structure that eliminates the need for and cost of one patterned photoresist layer.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 6, 2013
    Inventors: STEVEN ADLER, PETER JOHNSON, IRA OAKTREE WYGANT
  • Patent number: 8455963
    Abstract: A capacitive micromachined ultrasonic transducer (CMUT), which has a conductive structure that can vibrate over a cavity, has a number of vent holes that are formed in the bottom surface of the cavity. The vent holes eliminate the deflection of the CMUT membrane due to atmospheric pressure which, in turn, allows the CMUT to receive and transmit low frequency ultrasonic waves.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: June 4, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Steven Adler, Peter Johnson, Ira Oaktree Wygant
  • Patent number: 8455289
    Abstract: A capacitive micromachined ultrasonic transducer (CMUT), which has a conductive structure that can vibrate over a cavity, utilizes a thick oxide layer to substantially increase the volume of the cavity which, in turn, allows the CMUT to receive and transmit low frequency ultrasonic waves. In addition, the CMUT can include a back side bond pad structure that eliminates the need for and cost of one patterned photoresist layer.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: June 4, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Steven Adler, Peter Johnson, Ira Oaktree Wygant
  • Patent number: 8446237
    Abstract: A micro-electromechanical systems (MEMS) relay includes a switch with a first contact region and a second contact region that are vertically separated from each other by a gap. The MEMS relay requires a small vertical movement to close the gap and therefore is mechanically robust. In addition, the MEMS relay has a small footprint and, therefore, can be formed on top of small integrated circuits.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: May 21, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Dok Won Lee, Peter Johnson, Aditi Dutt Chaudhuri
  • Patent number: 8443511
    Abstract: A scalable MEMS inductor is formed on the top surface of a semiconductor die. The MEMS inductor includes a plurality of magnetic lower laminations, a circular trace that lies over and spaced apart from the magnetic lower laminations, and a plurality of upper laminations that lie over and spaced apart from the circular trace.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: May 21, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Peter Smeys, Peter Johnson
  • Publication number: 20130086205
    Abstract: Systems and methods for field data gathering and which provide flexible configuration options for a central office. The system, run from, mobile computing devices, provides a free-flowing data gathering experience while only requiring what the central office needs from the field. The central office can configure the system to accept different types of data by way of different data input means available to the mobile computing device. Only the data needed by the central office need be collected by the mobile device operator. The data format is defined by the central office and is uploaded to each of the relevant mobile computing devices for use by the operators. Once each data set has been collected by an operator, the data package with the data set is scheduled for transmission to the central office once a connection with the central office can be made.
    Type: Application
    Filed: September 30, 2011
    Publication date: April 4, 2013
    Applicant: SPIRA DATA CORP.
    Inventors: James St. Clair, Jon Watts, Karl Schulze, Peter Johnson
  • Patent number: 8407883
    Abstract: A damascene process is utilized to fabricate the segmented magnetic core elements of an integrated circuit inductor structure. The magnetic core is electroplated from a seed layer that is conformal with a permanent dielectric mold that results in sidewall plating defining an easy magnetic axis. The hard axis runs parallel to the longitudinal axis of the core and the inductor coils are orthogonal to the core's longitudinal axis. The magnetic field generated by the inductor coils is, therefore, parallel and self-aligned to the hard magnetic axis. The easy axis is enhanced by electroplating in an applied magnetic field parallel to the easy axis.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: April 2, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Peter Smeys, Peter Johnson, Andrei Papou
  • Publication number: 20130055502
    Abstract: An adjustable bed system includes a first frame having four actuators coupled thereto and disposed between the head and foot ends thereof. The actuators define a generally-rectangular configuration wherein first and third actuators are diagonally-opposed and wherein second and fourth actuators are diagonally-opposed. A second frame coupled to the first frame includes a first section secured to the first frame, a second section pivotably coupled to the first section towards the head end of the first frame, and a third section pivotably coupled to the first section towards the foot end of the first frame. The first and third actuators arc coupled to the second and third sections, respectively, for articulating the second and third sections, respectively. First and second leg assemblies are coupled to the second and fourth actuators, respectively, for selectively raising and lowering the first frame.
    Type: Application
    Filed: September 1, 2011
    Publication date: March 7, 2013
    Inventors: Norman A. Kay, Andrew Peter Johnson, Daniel DeSousa
  • Publication number: 20130049916
    Abstract: A galvanic die has signal structures and a transformer structure that provide galvanically-isolated signal and power paths for a high-voltage die and a low-voltage die, which are both physically supported by the galvanic die and electrically connected to the signal and transformer structures of the galvanic die.
    Type: Application
    Filed: August 26, 2011
    Publication date: February 28, 2013
    Inventors: Ann Gabrys, William French, Peter J. Hopper, Dok Won Lee, Peter Johnson
  • Publication number: 20130043970
    Abstract: An inductor device having an improved galvanic isolation layer arranged between a pair of coil and methods of its construction are described.
    Type: Application
    Filed: August 19, 2011
    Publication date: February 21, 2013
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Anindya PODDAR, Vijaylaxmi KHANOLKAR, Ashok S. PRABHU, Peter JOHNSON
  • Patent number: 8378460
    Abstract: Multiple wafers that each has multiple high-precision circuits and corresponding trim control circuits are batch trimmed in a process where each wafer is formed to include openings that expose trimmable circuit elements that are internal to the circuitry of the high-precision circuits. The high-precision circuits and trim control circuits are electrically activated during the trimming phase by metal traces that run along the saw streets. The method attaches a wafer contact structure to each wafer to electrically activate the metal traces. The method places the wafers with the wafer contact structures into a solution where the exposed trimmable circuit elements are electroplated or anodized when the actual output voltage of a high-precision circuit does not match the predicted output voltage of the high-precision circuit.
    Type: Grant
    Filed: December 24, 2010
    Date of Patent: February 19, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Peter Johnson, Peter Smeys, William French
  • Patent number: 8377792
    Abstract: An interdigitated semiconductor capacitor with a large number of plates and a capacitance in the micro-farad range is formed on a wafer with only a single lithography step by depositing each odd layer of metal through a first shadow mask that lies spaced apart from the wafer, and each even layer of metal through a second shadow mask that lies spaced apart from the wafer.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: February 19, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, William French, Peter Smeys, Peter Johnson
  • Patent number: 8378766
    Abstract: A micro-electromechanical systems (MEMS) relay includes a switch with a first contact region and a second contact region that are vertically separated from each other by a gap. The MEMS relay requires a small vertical movement to close the gap and therefore is mechanically robust. In addition, the MEMS relay has a small footprint and, therefore, can be formed on top of small integrated circuits.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: February 19, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Dok Won Lee, Peter Johnson, Aditi Dutt Chaudhuri
  • Patent number: 8378776
    Abstract: A galvanic die has signal structures and a transformer structure that provide galvanically-isolated signal and power paths for a high-voltage die and a low-voltage die, which are both physically supported by the galvanic die and electrically connected to the signal and transformer structures of the galvanic die.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: February 19, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Ann Gabrys, William French, Peter J. Hopper, Dok Won Lee, Peter Johnson
  • Patent number: 8324006
    Abstract: A method includes forming first isolation trenches in a first side of a first semiconductor-on-insulator (SOI) structure to electrically isolate multiple portions of the first SOI structure from each other. The method also includes bonding a second SOI structure to the first SOI structure to form multiple cavities between the SOI structures. The method further includes forming conductive plugs through a second side of the first SOI structure and forming second isolation trenches in the second side of the first SOI structure around the conductive plugs. In addition, the method includes removing portions of the second SOI structure to leave a membrane bonded to the first SOI structure. The isolated portions of the first SOI structure, the cavities, and the membrane form multiple capacitive micromachined ultrasonic transducer (CMUT) elements. Each CMUT element is formed in one of the isolated portions of the first SOI structure and includes multiple CMUT cells.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: December 4, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Steven J. Adler, Peter Johnson, Ira Wygant
  • Patent number: 8314676
    Abstract: A controlled seam magnetic core lamination utilizable in an inductor structure includes a magnetic base and first and second spaced-apart magnetic sidewalls extending substantially orthogonally from the base to define a seam therebetween.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: November 20, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Peter Smeys, Andrei Papou, Peter Johnson, Anuraag Mohan
  • Publication number: 20120280781
    Abstract: A controlled seam magnetic core lamination utilizable in an inductor structure includes a magnetic base and first and second spaced-apart magnetic sidewalls extending substantially orthogonally from the base to define a seam therebetween.
    Type: Application
    Filed: May 2, 2011
    Publication date: November 8, 2012
    Inventors: Peter Smeys, Andrei Papou, Peter Johnson, Anuraag Mohan
  • Publication number: 20120284144
    Abstract: A computer-implemented method for assessing fidelity of a product customization tool for an electronic catalog including electronic records representing a plurality of customizable products, the customizable products including a plurality of configurable option selections is described. The method includes identifying a plurality of test case grouping including one or more customizable products having defined ranges of the configurable option selection that do not affect a key output parameter for the grouping and identifying a set of test cases selected from the test case groupings, the test cases having selections associated with the configurable option selection. The method further includes evaluating the set of test cases relative to identify instances of products in the electronic catalog conforming to the selections associated with the configurable option selection and generating a report providing differences between what was expected with the number of rules and actual results of the evaluating act.
    Type: Application
    Filed: February 3, 2012
    Publication date: November 8, 2012
    Inventors: Nathan Herbst, Peter Johnson