Patents by Inventor Peter L. Kellerman

Peter L. Kellerman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040212946
    Abstract: An electrostatic clamp for securing a semiconductor wafer during processing. The electrostatic clamp comprises a base member, a resistive layer, a dielectric layer including a gas pressure distribution micro-groove network, a gas gap positioned between a backside of a semiconductor wafer and the dielectric layer, and a pair of high voltage electrodes positioned between the resistive layer and the dielectric layer. The electrostatic clamp can further comprise at least one ground electrode positioned between the resistive layer and the dielectric layer that provides shielding for the gas pressure distribution micro-groove network. The electrostatic clamp is characterized by a heat transfer coefficient of greater than or about 200 mW/Kcm2, a response time of less than or about 1 second, and gas leakage of less than or about 0.5 sccm.
    Type: Application
    Filed: April 22, 2003
    Publication date: October 28, 2004
    Inventors: Peter L. Kellerman, Victor Benveniste, Michel Pharand, Dale K. Stone
  • Publication number: 20040187788
    Abstract: The present invention is directed to a semiconductor thermal processing apparatus and a method for thermally cooling a semiconductor substrate. According to one aspect of the present invention, a gas-cooled clamp and associated method is disclosed which provides cooling of a substrate by thermal conduction generally in the free molecular regime. The gas-cooled clamp comprises a clamping plate having a plurality of protrusions that define gaps therebetween, wherein a distance or depth of the gaps are associated with a mean free path of the cooling gas therein. The gas-cooled clamp further comprises a pressure control system operable to control a backside pressure of the cooling gas within the plurality of gaps to thus control a heat transfer coefficient of the cooling gas, wherein the heat transfer coefficient of the cooling gas is primarily a function of the pressure and substantially independent of the gap distance.
    Type: Application
    Filed: March 28, 2003
    Publication date: September 30, 2004
    Inventors: Peter L. Kellerman, Victor M. Benveniste, Frederick M. Carlson
  • Patent number: 6735378
    Abstract: A thermal device with a container having a surface exposed to the substrate, wherein the container further has a heat source and a plurality of thermal shields situated between the surface exposed to the substrate and the heat source. The thermal shields are spaced from one another by a predetermined distance defining one or more gaps therebetween, wherein the predetermined distance is associated with a mean free path of a gas residing therein. Alternatively, the predetermined distance is variable. A pressure of a gas residing within the one or more gaps is controlled, wherein the pressure of the gas switches the thermal conductivity of the gas between generally conductive and generally non-conductive.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: May 11, 2004
    Assignee: Axcelis Technologies, Inc.
    Inventors: Peter L. Kellerman, Frederick M. Carlson
  • Publication number: 20040079289
    Abstract: An apparatus for processing a semiconductor wafer. The apparatus according to the present invention comprises a wafer port flange including an electrostatic chuck and a top plate including a lip. The electrostatic chuck defines a circumferential gas distribution groove and a gas gap positioned between a backside of a semiconductor wafer and the electrostatic chuck. The lip is positioned to shield an outside band of the wafer. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR §1.72(b).
    Type: Application
    Filed: October 23, 2002
    Publication date: April 29, 2004
    Inventors: Peter L. Kellerman, Kevin T. Ryan, Robert J. Mitchell
  • Patent number: 6458430
    Abstract: A method for use with a plasma immersion ion implantations systems wherein a substrate W having a patterned photoresist P thereon is implanted. The method includes ionizing a first gas in a chamber 12 to produce electrically inactive ions and reacting the electrically active ions with the photoresist P to produce outgassing 64. The outgassed material 64 is continuously evacuated until outgassing is substantially completed. The method further includes ionizing a second gas to produce electrically active ions and implanting a positively charged species of the electrically active ions into the substrate. Also disclosed is a method for curing the photoresist prior to ion implantation. A gas is ionized in the chamber 12 to produce positively and electrons. The electrons are first attracted to a substrate in the chamber having patterned photoresist P thereon for hardening the photoresist. The positively charged ions are then implanted into substrate W wherein photoresist outgassing is substantially prevented.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: October 1, 2002
    Assignee: Axcelis Technologies, Inc.
    Inventors: James D. Bernstein, Peter L. Kellerman, Alec S. Denholm
  • Patent number: 6305316
    Abstract: A wafer processing system is provided. The system includes a wafer handling system for introducing semiconductor wafers into a processing chamber. An oscillator is operatively coupled to an antenna for igniting a plasma within the processing chamber. The plasma and antenna form a resonant circuit with the oscillator, and the oscillator varies an output characteristic associated therewith based on a load change in the resonant circuit during plasma ignition.
    Type: Grant
    Filed: July 20, 2000
    Date of Patent: October 23, 2001
    Assignee: Axcelis Technologies, Inc.
    Inventors: William F. DiVergilio, Peter L. Kellerman, Kevin T. Ryan
  • Patent number: 6237527
    Abstract: A plasma immersion ion implantation method and system is provided for maintaining uniformity in implant energy distribution and for minimizing charge accumulation of an implanted substrate such as a wafer. A voltage modulator (27) applies a pulsed voltage signal (−Vp) to a platen (14) in a process chamber (17) containing a plasma, so that ions in the plasma are attracted by and implanted into a wafer residing on the platen. The voltage modulator (27) comprises: (i) a first switch (50) disposed between a power supply (48) and the platen for momentarily establishing a connection therebetween and supplying the pulsed voltage signal to the platen; (ii) a second switch (54) disposed between the platen (14) and ground for at least momentarily closing to discharge residual voltage (−Vr) from the platen after the first switch (50) opens and the connection between the power supply and the platen is broken; and (iii) a controller (56) for controlling sequential operation of the switches (50, 54).
    Type: Grant
    Filed: August 6, 1999
    Date of Patent: May 29, 2001
    Assignee: Axcelis Technologies, Inc.
    Inventors: Peter L. Kellerman, James D. Bernstein, A. Stuart Denholm
  • Patent number: 5909031
    Abstract: A plasma-enhanced electron shower (62) for an ion implantation system (10) is provided, including a target (64) provided with a chamber (84) at least partially defined by a replaceable graphite liner (82). A filament assembly (67) attached to the target generates and directs a supply of primary electrons toward a surface (118) provided by the graphite liner, which is biased to a low negative voltage of up to -10V (approximately -6V) to insure that secondary electrons emitted therefrom as a result of impacting primary electrons have a uniform low energy. The filament assembly (67) includes a filament (68) for thermionically emitting primary electrons; a biased (-300V) filament electrode (70) for focusing the emitted primary electrons, and a grounded extraction aperture (72) for extracting the focused primary electrons toward the graphite surface (118). A gas nozzle (77) attached to the target (64) introduces into the chamber a supply of gas molecules to be ionized by the primary electrons.
    Type: Grant
    Filed: September 8, 1997
    Date of Patent: June 1, 1999
    Assignee: Eaton Corporation
    Inventors: Peter L. Kellerman, James D. Bernstein, Brian S. Freer
  • Patent number: 5903009
    Abstract: A plasma-enhanced electron shower (62) for an ion implantation system (10) is provided, including an extension tube (66) having a replaceable graphite inner liner (88). The inner liner is biased to a low negative potential (-6 V) to prevent low energy secondary electrons generated by the electron shower target from being shunted away from the wafer, keeping them available for wafer charge neutralization. The electrically biased inner surface is provided with serrations (126) comprising alternating wafer-facing surfaces (128) and target-facing surfaces (130). During operation of the electron shower (62), photoresist or other material which may sputter back from the wafer collects on the wafer-facing surfaces (128), rendering them non-conductive, while the target-facing surfaces (130) remain clean and therefore conductive. The conductive target-facing surfaces provide a shunt (low resistance) path to electrical ground for high energy electrons generated in the electron shower.
    Type: Grant
    Filed: September 8, 1997
    Date of Patent: May 11, 1999
    Assignee: Eaton Corporation
    Inventors: James D. Bernstein, Brian S. Freer, Peter L. Kellerman
  • Patent number: 5856674
    Abstract: A ribbon filament (86) is provided for a thermionic emission device. The filament comprises an elongated body having a configuration defined by a length, a width, and a thickness. The length comprises a central portion (96) and first and second end portions (98) on either side of the central portion. The width of the central portion is greater than that of the first and second end portions. In addition, the thickness of the filament is substantially less than the width along its entire length. The ribbon filament (86) may be configured as a single helical coil having its first and second end portions (98) mounted to first and second legs (85), respectively, at locations of slots therein. Preferably, the filament (86) is comprised of tungsten and the first and second legs (85) are also comprised of tungsten.
    Type: Grant
    Filed: September 16, 1997
    Date of Patent: January 5, 1999
    Assignee: Eaton Corporation
    Inventor: Peter L. Kellerman
  • Patent number: 5780863
    Abstract: An electrostatic triode lens (36) is provided for use in an ion implantation system (10). The lens includes a terminal electrode (37) and an adjustable lens subassembly (40) comprising a suppression electrode (38) and a resolving electrode (39), each having matched curved surfaces (108, 110). The lens subassembly is positioned near the terminal electrode where the beam has a minimal waist in a first (dispersive) plane. Such positioning minimizes the required gaps between electrodes, and thus, helps minimize beam blow-up and the electron depletion region in the deceleration mode of operation. The suppression and resolving electrodes each have first and second portions (38A and 38B, 39A and 39B) separated by a gap (d38, d39). A movement mechanism (60, 62) simultaneously moves the first portions of the suppression and resolving electrodes (38A, 39A) toward and away from the second portions of the suppression and resolving electrodes (38B, 39B), respectively, to adjust the gaps (d38, d39) therebetween.
    Type: Grant
    Filed: April 29, 1997
    Date of Patent: July 14, 1998
    Assignee: Eaton Corporation
    Inventors: Victor M. Benveniste, Peter L. Kellerman
  • Patent number: 5198676
    Abstract: An ion beam intensity and emittance measuring system. A substrate supports conductive zones or regions that are impacted by an ion beam. Periodically the conductive regions are discharged through an integrator circuit which produces an output corresponding to the charge buildup on the conductive region. By determining the charge for multiple such regions impacted by an ion beam, a two-dimensional mapping of ion beam intensity vs. position is obtained on essentially a real-time basis. An emittance mask is also placed over the substrate and a measure of the emittance or spread of the ion beam is obtained.
    Type: Grant
    Filed: September 27, 1991
    Date of Patent: March 30, 1993
    Assignee: Eaton Corporation
    Inventors: Victor M. Benveniste, Peter L. Kellerman, John J. Schussler