Patents by Inventor Peter Lablans

Peter Lablans has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8209370
    Abstract: Apparatus and method for performing multi-value arithmetic operations are disclosed. Multi-value signals can be added, subtracted and multiplied using a first truth table to generate a residue and a second truth table to generate a carry. Additionally, method and apparatus to efficiently perform the function a0b1+a1b0 on multi-value signals are disclosed. Also an efficient method of processing large binary signals is disclosed.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: June 26, 2012
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans
  • Publication number: 20120149432
    Abstract: Methods for storing on a storage or memory medium, and retrieving, and displaying of multiple images in a registered manner, the images have been recorded concurrently. The images may comprise at least 2 video programs. A camera system for recording multiple concurrent images is also disclosed. Lenses and corresponding image sensors are calibrated to have calibrated and associated settings for recording multiple images that are substantially registered images. A registered image may be displayed on a single display. It may also be displayed on multiple displays. A camera for recording and displaying registered multiple images may be part of a mobile phone.
    Type: Application
    Filed: February 20, 2012
    Publication date: June 14, 2012
    Inventor: Peter Lablans
  • Patent number: 8201060
    Abstract: An encoder creates an (p,k,n) n-state codeword with p n-state symbols of which k n-state symbols are data symbols, an n-state symbol being represented by a signal with n>2, p>2 and k>(p?k). Intermediate states of an encoder in forward and in reverse direction are provided in a comparative n-state expression and implemented on a processor. A plurality of signals representing a codeword with at least one n-state symbol in error is processed by the processor by evaluating the comparative n-state expression. A partial result of an expression is determined after a symbol has been received. An error location and an error magnitude are determined. The error is corrected by the processor.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: June 12, 2012
    Assignee: Ternarylocig LLC
    Inventor: Peter Lablans
  • Patent number: 8180817
    Abstract: Methods for transposing elements of a sequence according to a rule, wherein the rule is derived from pseudo-noise or pseudo-noise like binary and non-binary sequences are disclosed. Sequences of transposed symbols can be recovered by applying a reversing rule. Sets of orthogonal hopping and transposition rules are created by applying transposition rules upon themselves. Sets of orthogonal hopping and transposition rules are also created from binary and non-binary Gold sequences.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: May 15, 2012
    Assignee: Temarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 8164655
    Abstract: Methods for storing on a storage or memory medium, and retrieving, and displaying of multiple images in a registered manner, the images have been recorded concurrently. The images may comprise at least 2 video programs. A camera system for recording multiple concurrent images is also disclosed. Lenses and corresponding image sensors are calibrated to have calibrated and associated settings for recording multiple images that are substantially registered images. A registered image may be displayed on a single display. It may also be displayed on multiple displays. A camera for recording and displaying registered multiple images may be part of a mobile phone.
    Type: Grant
    Filed: May 5, 2009
    Date of Patent: April 24, 2012
    Assignee: Spatial Cam LLC
    Inventor: Peter Lablans
  • Patent number: 8149143
    Abstract: Methods and apparatus for implementing an n-state ripple-adder scheme coder with n?2 using an n-state reversible switching function and a non-reversible n-state switching function acting upon a first and a second word of at least 2 n-state symbols are disclosed. Corresponding decoding methods and apparatus are also disclosed. A resulting codeword may be a codeword which can be decoded by using the identical or different n-state switching functions in a corresponding ripple adder scheme decoder. Feistel networks and LFSRs apply the coding and decoding. Systems using the coding and decoding methods may be communication, storage and/or financial systems.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: April 3, 2012
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 8103943
    Abstract: Symbol reconstruction methods by applying Galois Field arithmetic to Reed Solomon codewords have been disclosed. Reconstruction methods by applying n-valued reversing logic functions are also provided. A correct codeword can be selected from calculated codewords by comparing a calculated codeword with the Reed-Solomon codeword in error. A correct codeword can also be found by comparing a codeword in error with possible (p,k) codewords. Non Galois Field Reed Solomon coders are disclosed. Methods for correcting symbols in errors that have been identified as being in error are provided. Apparatus that implement the error correction methods are disclosed. Systems, including communication and storage systems that use the disclosed methods are also provided.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: January 24, 2012
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans
  • Publication number: 20110293062
    Abstract: A sequence generator implemented on a receiver is synchronized with a sequence generator at a transmitter. The receiver receives k n-state symbols, with k>1 and n>1 wherein each of the k n-state symbols is associated with a generating state of the sequence generator at the transmitter. A processor in the receiver evaluates an n-state expression that generates an n-state symbol that is associated with a synchronized state of the receiver. Coefficients related to the n-state expression are stored on a memory and are retrieved by the processor. The synchronized state in one embodiment is part of a code hop. The sequence generator in the receiver may be part of a descrambler, of a communication device, of a data storage device and/or of an opening mechanism.
    Type: Application
    Filed: May 31, 2011
    Publication date: December 1, 2011
    Applicant: Ternarylogic LLC
    Inventor: Peter Lablans
  • Publication number: 20110276854
    Abstract: An encoder creates an (p,k,n) n-state codeword with p n-state symbols of which k n-state symbols are data symbols, an n-state symbol being represented by a signal with n>2, p>2 and k>(p-k). Intermediate states of an encoder in forward and in reverse direction are provided in a comparative n-state expression and implemented on a processor. A plurality of signals representing a codeword with at least one n-state symbol in error is processed by the processor by evaluating the comparative n-state expression. A partial result of an expression is determined after a symbol has been received. An error location and an error magnitude are determined. The error is corrected by the processor.
    Type: Application
    Filed: May 9, 2011
    Publication date: November 10, 2011
    Applicant: Ternarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 8046661
    Abstract: Methods and apparatus for creating codewords of n-valued symbols with one or more n-valued check symbols are disclosed. Associating the codewords with a matrix allows for detection of one or more symbols in error and the location of such symbols in error. Methods to reconstruct symbols in error from other symbols not in error are also disclosed. Systems for using the methods of error detection and error correction by symbol reconstruction are also disclosed. Using two or more matrices to determine check symbols is also provided.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: October 25, 2011
    Assignee: Temarylogic LLC
    Inventor: Peter Lablans
  • Publication number: 20110214038
    Abstract: An encoder creates an (p,k,n) n-state codeword with p n-state symbols of which k n-state symbols are data symbols, an n-state symbol being represented by a signal with n>2, p>2 and k>(p?k). Intermediate states of an encoder in forward and in reverse direction are provided in a comparative n-state expression and implemented on a processor. A plurality of signals representing a codeword with at least one n-state symbol in error is processed by the processor by evaluating the comparative n-state expression. A partial result of an expression is determined after a symbol has been received. An error location and an error magnitude are determined. The error is corrected by the processor.
    Type: Application
    Filed: May 9, 2011
    Publication date: September 1, 2011
    Applicant: Ternarylogic LLC
    Inventor: Peter Lablans
  • Publication number: 20110182421
    Abstract: Methods for transposing elements of a sequence according to a rule, wherein the rule is derived from pseudo-noise or pseudo-noise like binary and non-binary sequences are disclosed. Sequences of transposed symbols can be recovered by applying a reversing rule. Sets of orthogonal hopping and transposition rules are created by applying transposition rules upon themselves. Sets of orthogonal hopping and transposition rules are also created from binary and non-binary Gold sequences.
    Type: Application
    Filed: April 7, 2011
    Publication date: July 28, 2011
    Applicant: Ternarylogic LLC
    Inventor: Peter Lablans
  • Publication number: 20110182423
    Abstract: Methods and apparatus for implementing an n-state ripple-adder scheme coder with n?2 using an n-state reversible switching function and a non-reversible n-state switching function acting upon a first and a second word of at least 2 n-state symbols are disclosed. Corresponding decoding methods and apparatus are also disclosed. A resulting codeword may be a codeword which can be decoded by using the identical or different n-state switching functions in a corresponding ripple adder scheme decoder. Feistel networks and LFSRs apply the coding and decoding. Systems using the coding and decoding methods may be communication, storage and/or financial systems.
    Type: Application
    Filed: April 11, 2011
    Publication date: July 28, 2011
    Inventor: Peter Lablans
  • Publication number: 20110170697
    Abstract: Reversible and self reversing multi-value scrambling functions created by applying multi-value inverters are disclosed. The generation of possible multi-value inverters is also presented. Corresponding multi-value descrambling functions are also disclosed. The multi-value functions are used in circuits that scramble and descramble multi-value signals. The multi-value functions can also be used in signal generators. Such signal generators do not require the use of multipliers. The auto-correlation of the signals generated by the signal generators is also presented. Electronic circuits that implement the multi-value functions are also described.
    Type: Application
    Filed: February 15, 2011
    Publication date: July 14, 2011
    Applicant: Ternarylogic LLC
    Inventor: Peter Lablans
  • Publication number: 20110098083
    Abstract: Methods and apparatus to create and display screen stereoscopic and panoramic images are disclosed. Methods and apparatus are provided to generate multiple images that are combined into a stereoscopic or a panoramic image. An image may be a static image. It may also be a video image. A controller provides correct camera settings for different conditions. An image processor creates a stereoscopic or a panoramic image from the correct settings provided by the controller. A plurality of lens/sensor units is placed on a carrier. Lens/sensor units are rotationally aligned. A controller rotationally aligns images of lens/sensor units that are rotationally misaligned.
    Type: Application
    Filed: December 31, 2010
    Publication date: April 28, 2011
    Inventor: Peter Lablans
  • Patent number: 7930331
    Abstract: Methods for transposing elements of a sequence according to a rule, wherein the rule is derived from pseudo-noise or pseudo-noise like binary and non-binary sequences are disclosed. Sequences of transposed symbols can be recovered by applying a reversing rule. Sets of orthogonal hopping and transposition rules are created by applying transposition rules upon themselves. Sets of orthogonal hopping and transposition rules are also created from binary and non-binary Gold sequences.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: April 19, 2011
    Assignee: Temarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 7924176
    Abstract: Methods and apparatus for implementing an n-state ripple-adder scheme coder with n?2 using an n-state reversible switching function and a non-reversible n-state switching function acting upon a first and a second word of at least 2 n-state symbols are disclosed. Corresponding decoding methods and apparatus are also disclosed. A resulting codeword may be a codeword which can be decoded by using the identical or different n-state switching functions in a corresponding ripple adder scheme decoder. Feistel networks and LFSRs apply the coding and decoding. Systems using the coding and decoding methods may be communication, storage and/or financial systems.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: April 12, 2011
    Inventor: Peter Lablans
  • Publication number: 20110064214
    Abstract: Methods and apparatus for coding and decoding n-state symbols with n?2 and n>2 and n>3 and n>4 are provided wherein at least one implementation of an addition over an alternate finite field GF(n) and an inverter defined by a multiplication over the alternate finite field GF(n) are provided. Encoders and decoders implementing a single n-state truth table that is a truth table of an addition over an alternate finite field GF(n) modified in accordance with at least one inverter defined by a multiplication over the alternate finite field GF(n) are also provided. Encoders include scramblers, Linear Feedback Shift Register (LFSR) based encoders, sequence generator based encoders, block coders, streaming cipher encoders, transposition encoders, hopping rule encoders, Feistel network based encoders, check symbol based encoders, Hamming coder, error correcting encoders, encipherment encoders, Elliptic Curve Coding encoders and all corresponding decoders.
    Type: Application
    Filed: November 23, 2010
    Publication date: March 17, 2011
    Applicant: Ternarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 7877670
    Abstract: The invention relates to error-correcting coding and correct restart of decoding after errors of sequences that are coded by convolutional coders or LFSR based descramblers. The signals can be binary or multi-valued signals. Methods and apparatus to convolutional encode and decode sequences of binary and n-valued symbols are disclosed. The invention further discloses methods and apparatus to identify symbols in error in sequences coded according to methods of the invention. Methods and apparatus to correct these errors are provided. Methods and apparatus to repair errors in a Trellis of received sequences are also provided. Methods and apparatus for n-valued Recursive Systematic Convolutional coders and decoders are disclosed.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: January 25, 2011
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 7864079
    Abstract: Ternary (3-value) and higher, multi-value digital scramblers/descramblers in digital communications. The method and apparatus of the present invention includes the creation of ternary (3-value) and higher value truth tables that establish ternary and higher value scrambling functions which are its own descrambling functions. The invention directly codes by scrambling ternary and higher-value digital signals and directly decodes by descrambling with the same function. A disclosed application of the invention is the creation of composite ternary and higher-value scrambling devices and methods consisting of single scrambling devices or functions combined with ternary or higher value shift registers. Another disclosed application is the creation of ternary and higher-value spread spectrum digital signals. Another disclosed application is a composite ternary or higher value scrambling system, comprising an odd number of scrambling functions and the ability to be its own descrambler.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: January 4, 2011
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans