Patents by Inventor Peter Lablans

Peter Lablans has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7865807
    Abstract: Methods and systems for error detection and error correction in n-valued with n>2 data symbols are disclosed. N-valued check symbols are generated from data symbols in n-valued logic expressions using n-valued logic functions. N-valued Hamming codes are disclosed. Also disclosed is the generation of check symbols from data symbols in an n-valued expression wherein at least one check symbol is multiplied by a factor not equal to 0 or 1 in GF(n). Identifying n-valued symbols in error by check symbols and error correction by solving sets of independent n-valued equations are also disclosed. A method for introducing and removing annoyance errors is provided. Systems for error corrections in communication and data storage are also provided.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: January 4, 2011
    Inventor: Peter Lablans
  • Patent number: 7865806
    Abstract: Methods and apparatus reducing the number of multipliers in Galois Field arithmetic are disclosed. Methods and apparatus for implementing n-valued Linear Feedback Shift Register (LFSR) based applications with a reduced number of multipliers are also disclosed. N-valued LFSRs with reduced numbers of multipliers in Fibonacci and in Galois configuration are demonstrated. Multiplier reduction methods are extended to n-valued functions with more than 2 inputs. Methods to create multiplier reduced multi-input n-valued function truth tables are disclosed. Methods and apparatus to implement these truth tables with a limited number of n-valued inverters are also disclosed. Scrambler/descrambler combinations with adders and multipliers over GF(2p) are provided. Communication, data storage and digital rights management systems using multiplier reduction methods and apparatus or the disclosed scrambler/descrambler combination are also provided.
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: January 4, 2011
    Inventor: Peter Lablans
  • Patent number: 7864087
    Abstract: A method for coding a message of a plurality of m-state symbols into a coded message of n-state symbols wherein n>m is disclosed. A method to make the distribution of states of n-state symbols a uniform distribution is also disclosed. A coding rule is initiated based on a distribution of states of m-state symbols. A method of coding the coding rule by transposition is also provided. In one embodiment a coded message of n-state symbols has symbols that each have a unique state. A system for executing the coding and decoding methods is also disclosed.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: January 4, 2011
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans
  • Publication number: 20100322414
    Abstract: Ternary (3-value) and higher, multi-value digital scramblers/descramblers in digital communications. The method and apparatus of the present invention includes the creation of ternary (3-value) and higher value truth tables that establish ternary and higher value scrambling functions which are its own descrambling functions. The invention directly codes by scrambling ternary and higher-value digital signals and directly decodes by descrambling with the same function. A disclosed application of the invention is the creation of composite ternary and higher-value scrambling devices and methods consisting of single scrambling devices or functions combined with ternary or higher value shift registers. Another disclosed application is the creation of ternary and higher-value spread spectrum digital signals. Another disclosed application is a composite ternary or higher value scrambling system, comprising an odd number of scrambling functions and the ability to be its own descrambler.
    Type: Application
    Filed: August 26, 2010
    Publication date: December 23, 2010
    Applicant: Ternarylogic LLC
    Inventor: Peter Lablans
  • Publication number: 20100299579
    Abstract: Convolutional coders having an n-state with n?2 Linear Feedback Shift Registers (LFSR) in Galois configuration with k shift register elements with k>1 are provided. Corresponding decoders are also provided. A convolutional coder generates a sequence of coded n-state symbols. A content of a starting position of an LFSR in a decoder is determined when sufficient error free coded symbols are available. Up to k symbols in error are corrected. A systematic convolutional coder and decoder are also provided.
    Type: Application
    Filed: May 5, 2010
    Publication date: November 25, 2010
    Applicant: Ternarylogic LLC
    Inventor: Peter Lablans
  • Publication number: 20100271243
    Abstract: Methods and apparatus for implementing an n-state ripple-adder scheme coder with n?2 using an n-state reversible switching function and a non-reversible n-state switching function acting upon a first and a second word of at least 2 n-state symbols are disclosed. Corresponding decoding methods and apparatus are also disclosed. A resulting codeword may be a codeword which can be decoded by using the identical or different n-state switching functions in a corresponding ripple adder scheme decoder. Feistel networks and LFSRs apply the coding and decoding. Systems using the coding and decoding methods may be communication, storage and/or financial systems.
    Type: Application
    Filed: June 30, 2010
    Publication date: October 28, 2010
    Applicant: Ternarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 7782089
    Abstract: N-valued re-circulating latches using n-valued reversible inverters with n>3 are disclosed. Latches using n-valued self-reversing inverters are provided; latches using n-valued universal inverters are provided; and latches using inverters which are not self-reversing or universal are also provided. A latch may use two individually controlled gates. It may also use one individually controlled gate. N-valued latches are provided wherein a state is represented by a signal being an independent instance of a physical phenomenon. A latch not using absence-of-signal as a state is also provided.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: August 24, 2010
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans
  • Publication number: 20100211803
    Abstract: Method and apparatus for writing scrambled multi-value data to a physical media and for reading scrambled multi-value data from a physical media, are disclosed. The physical media can be an optical disk. The scrambling can be performed by a multi-valued LFSR scrambler and the descrambling can be performed by a multi-valued LFSR descrambler. Further, the multi-valued data that is scrambled can include synchronization data and/or user data. Error correction coding can be used during the writing process and processing to correct for errors can be used during the reading process. Also, methods and apparatus for synchronizing multi-valued data written to and read from physical media are disclosed. Multi-value correlation methods and apparatus are also disclosed.
    Type: Application
    Filed: April 12, 2010
    Publication date: August 19, 2010
    Applicant: Ternarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 7772999
    Abstract: Methods and apparatus for implementing an n-state ripple-adder scheme coder with n?2 using an n-state reversible switching function and a non-reversible n-state switching function acting upon a first and a second word of at least 2 n-state symbols are disclosed. Corresponding decoding methods and apparatus are also disclosed. A resulting codeword may be a codeword which can be decoded by using the identical or different n-state switching functions in a corresponding ripple adder scheme decoder. Feistel networks and LFSRs apply the coding and decoding. Systems using the coding and decoding methods may be communication, storage and/or financial systems.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: August 10, 2010
    Inventor: Peter Lablans
  • Publication number: 20100180097
    Abstract: Methods and apparatus to implement LFSRs and LFSR based sequence generators, detectors, scramblers and descramblers by addressable memory are disclosed. The methods and apparatus may be processing binary or n-valued symbols, with n>2. Methods to uniquely characterize n-valued Gold sequence are also disclosed. Self-synchronizing methods to detect sequences which can be decomposed into unique words are also disclosed. Methods and apparatus to implement Fibonacci and Galois LFSRs are disclosed.
    Type: Application
    Filed: March 24, 2010
    Publication date: July 15, 2010
    Applicant: Ternarylogic LLC
    Inventor: Peter Lablans
  • Publication number: 20100164548
    Abstract: An n-valued switch with n?2 and n>2 and n>7, with an input enabled to receive a signal in one of n states, an output enabled to provide a signal in one of at least 2 states, under control of a control signal having one of at least 2 states is disclosed. Signals are instances of a physical phenomenon, an instance representing a state. N-valued inverters are also disclosed. Different types of signals are disclosed, including optical signals with different wavelengths, electrical signals with different frequencies and signals represented by a presence of a material. A kit including an n-valued switch is also disclosed.
    Type: Application
    Filed: February 23, 2010
    Publication date: July 1, 2010
    Applicant: Ternarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 7725779
    Abstract: Method and apparatus for writing scrambled multi-value data to a physical media and for reading scrambled multi-value data from a physical media, are disclosed. The physical media can be an optical disk. The scrambling can be performed by a multi-valued LFSR scrambler and the descrambling can be performed by a multi-valued LFSR descrambler. Further, the multi-valued data that is scrambled can include synchronization data and/or user data. Error correction coding can be used during the writing process and processing to correct for errors can be used during the reading process. Also, methods and apparatus for synchronizing multi-valued data written to and read from physical media are disclosed. Multi-value correlation methods and apparatus are also disclosed.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: May 25, 2010
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans
  • Publication number: 20100109922
    Abstract: A method for coding a message of a plurality of m-state symbols into a coded message of n-state symbols wherein n>m is disclosed. A method to make the distribution of states of n-state symbols a uniform distribution is also disclosed. A coding rule is initiated based on a distribution of states of m-state symbols. A method of coding the coding rule by transposition is also provided. In one embodiment a coded message of n-state symbols has symbols that each have a unique state. A system for executing the coding and decoding methods is also disclosed.
    Type: Application
    Filed: December 21, 2009
    Publication date: May 6, 2010
    Applicant: Temarylogic LLC
    Inventor: Peter Lablans
  • Publication number: 20100097444
    Abstract: Methods and apparatus to create and display stereoscopic and panoramic images are disclosed. Apparatus is provided to control the position of a lens in relation to a reference lens. Methods and apparatus are provided to generate multiple images that are combined into a stereoscopic or a panoramic image. An image may be a static image. It may also be a video image. A controller provides correct camera settings for different conditions. An image processor creates a stereoscopic or a panoramic image from the correct settings provided by the controller. A panoramic video wall system is also disclosed.
    Type: Application
    Filed: December 9, 2009
    Publication date: April 22, 2010
    Inventor: Peter Lablans
  • Publication number: 20100097443
    Abstract: Methods and apparatus to create and display panoramic images on a mobile device are disclosed. Such a mobile device can be a mobile phone. Apparatus is provided to control the position of a lens in relation to a reference lens. Methods and apparatus are provided to generate multiple images that are combined into a panoramic image. A panoramic image may be a static image. It may also be a video image. A controller provides correct camera settings for different conditions. An image processor creates a panoramic image from the correct settings provided by the controller. A panoramic camera is applied in a computer gaming system.
    Type: Application
    Filed: August 10, 2009
    Publication date: April 22, 2010
    Inventor: Peter Lablans
  • Publication number: 20100097442
    Abstract: Methods and apparatus to create and display panoramic images on a mobile device are disclosed. Such a mobile device can be a mobile phone. Apparatus is provided to control the position of a lens in relation to a reference lens. Methods and apparatus are provided to generate multiple images that are combined into a panoramic image. A panoramic image may be a static image. It may also be a video image. A controller provides correct camera settings for different conditions. An image processor creates a panoramic image from the correct settings provided by the controller. A panoramic camera is applied in a computer gaming system.
    Type: Application
    Filed: May 7, 2009
    Publication date: April 22, 2010
    Inventor: Peter Lablans
  • Patent number: 7696785
    Abstract: An n-valued switch with n?2, with an input enabled to receive a signal in one of n states, an output enabled to provide a signal in one of at least 2 states, under control of a control signal having one of at least 2 states is disclosed. Signals are instances of a physical phenomenon, an instance representing a state. N-valued inverters are also disclosed. Different types of signals are disclosed, including optical signals with different wavelengths, electrical signals with different frequencies and signals represented by a presence of a material. A kit including an n-valued switch is also disclosed.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: April 13, 2010
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans
  • Publication number: 20100085802
    Abstract: N-valued re-circulating latches using n-valued reversible inverters with n>3 are disclosed. Latches using n-valued self-reversing inverters are provided; latches using n-valued universal inverters are provided; and latches using inverters which are not self-reversing or universal are also provided. A latch may use two individually controlled gates. It may also use one individually controlled gate. N-valued latches are provided wherein a state is represented by a signal being an independent instance of a physical phenomenon. A latch not using absence-of-signal as a state is also provided.
    Type: Application
    Filed: December 10, 2009
    Publication date: April 8, 2010
    Applicant: Temarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 7659839
    Abstract: A method for coding a message of a plurality of m-state symbols into a coded message of n-state symbols wherein n>m is disclosed. A method to make the distribution of states of n-state symbols a uniform distribution is also disclosed. A coding rule is initiated based on a distribution of states of m-state symbols. A method of coding the coding rule by transposition is also provided. In one embodiment a coded message of n-state symbols has symbols that each have a unique state. A system for executing the coding and decoding methods is also disclosed.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: February 9, 2010
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 7656196
    Abstract: N-valued re-circulating latches using n-valued reversible inverters with n>3 are disclosed. Latches using n-valued self-reversing inverters are provided; latches using n-valued universal inverters are provided; and latches using inverters which are not self-reversing or universal are also provided. A latch may use two individually controlled gates. It may also use one individually controlled gate. N-valued latches are provided wherein a state is represented by a signal being an independent instance of a physical phenomenon. A latch not using absence-of-signal as a state is also provided.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: February 2, 2010
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans