Abstract: The memory cells with floating gates are tested by applying voltage surges to the source or the drain of a selection transistor.

Abstract: A memory configuration has at least two memories connected to one another. In the event of a memory cell access, it is ascertained in a comparison circuit of the first memory whether the address applied to a first communications interface of the memory corresponds to an address of data stored in the first memory. In the event of non-correspondence of the addresses, the address of the requested data is transferred by a control circuit via a second communications interface, which can be operated independently of the first communications interface, to the second identical memory. The requested data are received from the second memory via the second communications interface of the first memory and output via the first communications interface of the first memory. Point-to-point connections enable a high data transfer rate of the memory configuration and hence a high data throughput with good signal quality.

Abstract: An active surface with a source area, a channel area and a drain area is provided in a semiconductor substrate. Each of the areas lie adjacent to a main surface of the semiconductor substrate. At least one trench is provided in the main surface of the semiconductor substrate. The trench is adjacent to the channel area and is situated in the gate electrode part. The gate electrode preferably has two opposite parts which are each adjacent to the channel area. The transistor is produced using standard process steps.

Abstract: The system enables testing fast synchronous semiconductor circuits, particularly semiconductor memory chips. Various test signals such as test data, data strobe signals, control/address signals are combined to form signal groups and controllable transmit driver and receiver elements allocated to them are in each case jointly activated or, respectively, driven by timing reference signals generated by programmable DLL delay circuits. A clock signal generated in a clock generator in the BOST semiconductor circuit is picked up at a tap in the immediate vicinity of the semiconductor circuit chip to be tested and fed back to a DLL circuit in the BOST chip where it is used for eliminating delay effects in the lines leading to the DUT and back to the BOST.

Abstract: The novel address counter can be used in combination with an existing test unit—serving for testing digital circuits—for addressing synchronous high-frequency digital circuits, in particular fast memory devices. Address offset values are provided in programmable offset registers, with a multiplexer circuit and a selection and combination circuit, on the basis of input signals which are fed in at low frequency and in parallel by the test unit. Simple address changes and address jumps can be realized at a high clock frequency in a very flexible manner.

Abstract: A circuit configuration for generating control signals for testing high-frequency synchronous digital circuits, especially memory chips, is described. A p-stage shift register which is clocked at a clock frequency corresponding to the high clock frequency of the digital circuit to be tested has connected to its parallel loading inputs p logical gates which logically combine a static control word with a dynamic n-position test word. The combined logical value is loaded into the shift register at a low-frequency loading clock rate so that a control signal, the value of which depends on the information loaded into the shift register in each clock cycle of the clock frequency of the latter is generated at the serial output of the shift register.

Abstract: The invention relates to a system for testing fast integrated digital circuits, in particular semiconductor modules, such as for example SDRAMs. In order to achieve the necessary chronological precision in the testing even of DDR-SDRAMs, with at the same time the high degree of parallelism of the test system required for mass production, an additional semiconductor circuit module (BOST module) is inserted into the signal path between a standard testing device and the SDRAM to be tested. This additional module is set up so as to multiply the relatively slow clock frequency of the conventional testing device, and to determine the signal sequence for control signals, addresses, and data background with which the SDRAM module is tested, dependent on signals of the testing device and also on register contents, programmed before the test, in the BOST module.

Abstract: The method and the device generate digital signal patterns. Signal patterns or signal pattern groups are stored in a very small buffer register. The position of a following signal pattern or following signal pattern group is also stored in the form of a branch address, together with each signal pattern or each signal pattern group. A simple control logic circuit receives a control signal and determines whether the content of the currently addressed group is output continuously or the following group given by the branch address stored in the register is output after the currently selected group has been completely output. The novel method and device can advantageously be used for testing semiconductor memories and implemented in a cost-effective semiconductor circuit which is remote from a conventional test system.

Abstract: A method and a configuration are provided for compensating for parasitic current losses in an MRAM memory cell array. Individual word lines and bit lines are supplied with currents which are proportioned in such a way that a total current level at respective points of intersection between the word lines and the bit lines is substantially constant.

Abstract: A magneto-resistive random access memory (MRAM) configuration is described in which a plurality of memory cell blocks are supplied with operating voltages that differ from one another in each case. This results in that the chip voltage supply of about 2 to 3 V can be better utilized. The memory cell blocks are formed of memory cells disposed at cross-over points of word lines and bit lines.

Abstract: One electrode of each storage capacitor C of the memory cells MC is connected via the associated memory transistor T to one of the bit lines BLi and another electrode is connected to one of the plate segments PLA, PLB; PLC, PLD. A control terminal of each selection transistor T is connected to one of the word lines WLi. In a normal operating mode, the potential of only one of the plate segments in each case is pulsed in the event of accesses to the memory cells MC. In a test operating mode, the potentials of both plate segments are pulsed simultaneously.

Abstract: Memory cells are arranged at crossover points of word lines WLi and bit lines. First reference cells are arranged at crossover points of at least one first reference word line and bit lines. In a normal operating mode, the reference cells serve for generating a reference potential on the bit lines prior to a readout of the memory cells. Second reference cells are arranged at crossover points of at least one second reference word line and the bit lines. In a test operating mode, the second reference cells serve for generating a reference potential on the bit lines prior to a readout of the reference cells.

Abstract: The integrated dynamic semiconductor memory has memory cells which are combined to form individually addressable normal units and redundant units. The redundant units are used to replace faulty normal units. The address of a normal unit to be replaced is in each case stored in memory units. A self-test unit carries out a functional test of the memory cells with a defined memory-retention time for the memory cell contents, and an analysis as to which of the normal units are to be replaced by which of the redundant units. The memory units are programmed in accordance with the analysis result, and the memory-retention time is increased following the programming. The functional test, the analysis and the programming are repeated until all the memory units have been programmed. This makes it possible to achieve a high quality semiconductor memory in terms of its memory-retention time for the memory cell contents, with a comparatively low test and repair effort.

Abstract: The memory cells with floating gates are tested by applying voltage surges to the source or the drain of a selection transistor.

Abstract: A semiconductor memory configuration, in particular a DRAM, in which redundant memory cells, bit lines and word lines are determined for failed memory cells, failed word lines and failed bit lines by a built-in-self-test computing unit and a special algorithm.

Abstract: The present invention relates to an integrated circuit which is connected to a reference-ground potential and to a supply potential. Since differing activity in the integrated circuit results in a fluctuating current being drawn by the integrated circuit, current surges may arise on the supply potential. To prevent current surges on the supply potential, a controllable load is produced together with the integrated circuit, with the result that the power drawn by the combination of integrated circuit and the load is approximately constant.

Abstract: A configuration for testing chips includes a printed circuit board having conductive probe needles to electrically connect the printed circuit board to chips and for testing the chips on the printed circuit board in parallel, some of the probe needles configured as dummy needles for mechanically self-aligning the chips. The board is configured closely to the application such that many chips (1) can be tested simultaneously in parallel. The chips can have markings or depressions to be engaged with free ends of the dummy needles remote from the board. Adapters can be disposed between the probe needles and the chips. Also, the chips can have structures disposed thereon between the probe needles and the chips. The board can have alignment aids for orienting the chips.