Patents by Inventor Peter Rabkin

Peter Rabkin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11721727
    Abstract: A memory device includes a silicon-germanium source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the silicon-germanium source contact layer, and a memory stack structure vertically extending through the alternating stack. The memory stack structure comprises a memory film and a vertical semiconductor channel that contacts the memory film. The silicon-germanium source contact layer contacts a cylindrical portion of an outer sidewall of the vertical semiconductor channel. Logic circuits for operating the memory elements may be provided on a substrate within a same semiconductor die, or may be provided in another semiconductor die that is bonded to the semiconductor die containing the memory device.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: August 8, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ashish Baraskar, Raghuveer S. Makala, Peter Rabkin
  • Patent number: 11676954
    Abstract: A semiconductor structure includes a memory die bonded to a logic die. The memory die includes an alternating stack of insulating layers and electrically conductive layers; memory openings extending through the alternating stack, memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective memory film, a source layer contacting the vertical semiconductor channels, a backside isolation dielectric layer contacting a backside surface of the source layer, and a source power supply mesh including a planar portion of a source-side electrically conductive layer that is located on a backside of the backside isolation dielectric layer and electrically connected to the source layer by conductive material portions that extend through the backside isolation dielectric layer.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: June 13, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Peter Rabkin, Masaaki Higashitani, Kwang-ho Kim
  • Patent number: 11646283
    Abstract: A first metal layer can be deposited over first dielectric material layers of a first substrate, and can be patterned into first bonding pads. A first low-k material layer can be formed over the first bonding pads. The first low-k material layer includes a low-k dielectric material such as a MOF dielectric material or organosilicate glass. A second semiconductor die including second bonding pads can be provided. The first bonding pads are bonded to the second bonding pads to form a bonded assembly.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: May 9, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Lin Hou, Peter Rabkin, Masaaki Higashitani, Ramy Nashed Bassely Said
  • Patent number: 11646282
    Abstract: A bonded assembly includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes first metallic bonding pads embedded in first dielectric material layers, the second semiconductor die includes second metallic bonding pads embedded in second dielectric material layers, the first metallic bonding pads are bonded to a respective one of the second metallic bonding pads; and each of the first metallic bonding pads includes a corrosion barrier layer containing an alloy of a primary bonding metal and at least one corrosion-suppressing element that is different from the primary bonding metal.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: May 9, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Lin Hou, Peter Rabkin, Masaaki Higashitani
  • Patent number: 11646081
    Abstract: Technology is provided for extending the useful life of a block of memory cells by changing an operating parameter in a physical region of the block that is more susceptible to wear than other regions. Changing the operating parameter in the physical region extends the life of that region, which extends the life of the block. The operating parameter may be, for example, a program voltage step size or a storage capacity of the memory cells. For example, using a smaller program voltage step size in a sub-block that is more susceptible to wear extends the life of that sub-block, which extends the life of the block. For example, programming memory cells to fewer bits per cell in the region of the block (e.g., sub-block, word line) that is more susceptible to wear extends the useful life of that region, which extends the life of the block.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: May 9, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Peter Rabkin, Henry Chin, Ken Oowada, Dengtao Zhao, Gerrit Jan Hemink
  • Publication number: 20230042438
    Abstract: A bonded assembly includes a first semiconductor die and a second semiconductor die that are bonded to each other by dielectric-to-dielectric bonding. First conductive via structures vertically extend through the second semiconductor die and a respective subset of the first dielectric material layers in the first semiconductor die, and contact a respective first metal interconnect structure in the first semiconductor die. Second conductive via structures vertically extend through a second substrate and a respective subset of the second dielectric material layers in the second semiconductor die, and contacting a respective second metal interconnect structure in the second semiconductor die. Redistribution metal interconnect structures located over a backside surface of the second substrate electrically connect the first conductive via structures and the second conductive via structures, and provide electrical interconnection between the first semiconductor die and the second semiconductor die.
    Type: Application
    Filed: August 6, 2021
    Publication date: February 9, 2023
    Inventors: Lin Hou, Peter Rabkin, Yangyin Chen, Masaaki Higashitani
  • Publication number: 20230041476
    Abstract: Technology is provided for extending the useful life of a block of memory cells by changing an operating parameter in a physical region of the block that is more susceptible to wear than other regions. Changing the operating parameter in the physical region extends the life of that region, which extends the life of the block. The operating parameter may be, for example, a program voltage step size or a storage capacity of the memory cells. For example, using a smaller program voltage step size in a sub-block that is more susceptible to wear extends the life of that sub-block, which extends the life of the block. For example, programming memory cells to fewer bits per cell in the region of the block (e.g., sub-block, word line) that is more susceptible to wear extends the useful life of that region, which extends the life of the block.
    Type: Application
    Filed: August 3, 2021
    Publication date: February 9, 2023
    Applicant: SanDisk Technologies LLC
    Inventors: Xiang Yang, Peter Rabkin, Henry Chin, Ken Oowada, Dengtao Zhao, Gerrit Jan Hemink
  • Patent number: 11569215
    Abstract: A semiconductor structure includes at least one set of vertical field effect transistors embedded within dielectric material layers overlying a substrate. Each vertical field effect transistor includes a bottom doped semiconductor electrode, a vertical transistor channel, a cylindrical gate dielectric, and a top doped semiconductor electrode. A three-dimensional NAND memory array can be provided over the first field effect transistors, and can be electrically connected to the vertical field effect transistors via metal interconnect structures. Alternatively, a three-dimensional NAND memory array can be formed on another substrate, which can be bonded to the substrate via metal-to-metal bonding. The vertical field effect transistors can be employed as switches for bit lines, word lines, or other components of the three-dimensional NAND memory array.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: January 31, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kwang-Ho Kim, Peter Rabkin
  • Patent number: 11562975
    Abstract: A bonded assembly of a first semiconductor die and a second semiconductor die includes first and second semiconductor dies. The first semiconductor die includes first semiconductor devices, first metal interconnect structures embedded in first dielectric material layers, and first metal bonding pads laterally surrounded by a semiconductor material layer. The second semiconductor die includes second semiconductor devices, second metal interconnect structures embedded in second dielectric material layers, and second metal bonding pads that include primary metal bonding pads and auxiliary metal bonding pads. The auxiliary metal bonding pads are bonded to the semiconductor material layer through metal-semiconductor compound portions formed by reaction of surface portions of the semiconductor material layer and an auxiliary metal bonding pad. The primary metal bonding pads are bonded to the first metal bonding pads by metal-to-metal bonding.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: January 24, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Lin Hou, Peter Rabkin, Masaaki Higashitani
  • Publication number: 20230008286
    Abstract: A bonded assembly includes a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads laterally surrounded by a first pad-level dielectric layer. The first pad-level dielectric layer includes at least one first encapsulated airgap located between neighboring pairs of first bonding pads and encapsulated by a first dielectric fill material of the first pad-level dielectric layer. The bonded assembly includes a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads laterally surrounded by a second pad-level dielectric layer. Each of the second bonding pads is bonded to a respective one of the first bonding pads.
    Type: Application
    Filed: July 8, 2021
    Publication date: January 12, 2023
    Inventors: Lin HOU, Peter RABKIN, Adarsh RAJASHEKHAR, Raghuveer S. MAKALA, Masaaki HIGASHITANI
  • Patent number: 11538828
    Abstract: A memory device can include a strained single-crystalline silicon layer and an alternating stack of insulating layers and electrically conductive layers located over the strained single-crystalline silicon layer. A memory opening fill structure extending through the alternating stack may include an epitaxial silicon-containing pedestal channel portion, and a vertical semiconductor channel, and a vertical stack of memory elements located adjacent to the vertical semiconductor channel. Additionally or alternatively, a drain region can include a semiconductor drain portion and a nickel-aluminum-semiconductor alloy drain portion.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: December 27, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ashish Baraskar, Raghuveer S. Makala, Peter Rabkin
  • Patent number: 11508748
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and a memory stack structure vertically extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel and a memory film. The vertical semiconductor channel can include a III-V compound semiconductor channel material. A III-V compound substrate semiconductor layer or a III-V compound semiconductor source region can be used to provide low-resistance electrical connection to a bottom end of the vertical semiconductor channel, and a drain region including a graded III-V compound semiconductor material can be used to provide low-resistance electrical connection to a top end of the vertical semiconductor channel.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: November 22, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ashish Baraskar, Peter Rabkin, Raghuveer S. Makala
  • Patent number: 11508654
    Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: November 22, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Luisa Lin, Mohan Dunga, Venkatesh P. Ramachandra, Peter Rabkin, Masaaki Higashitani
  • Publication number: 20220367393
    Abstract: A semiconductor structure includes a bonded assembly of a first semiconductor die including first metal bonding pads and a second semiconductor die including second metal bonding pads, and a capacitor structure including a first electrode, a second electrode, and a node dielectric. The first electrode includes first bonded pairs of metal bonding pads. The second electrode includes second bonded pairs of metal bonding pads. The node dielectric includes portions dielectric material layers laterally surrounding the metal bonding pads.
    Type: Application
    Filed: May 11, 2021
    Publication date: November 17, 2022
    Inventors: Shiqian SHAO, Fumiaki TOYAMA, Peter RABKIN
  • Patent number: 11495613
    Abstract: A memory device can include a strained single-crystalline silicon layer and an alternating stack of insulating layers and electrically conductive layers located over the strained single-crystalline silicon layer. A memory opening fill structure extending through the alternating stack may include an epitaxial silicon-containing pedestal channel portion, and a vertical semiconductor channel, and a vertical stack of memory elements located adjacent to the vertical semiconductor channel Additionally or alternatively, a drain region can include a semiconductor drain portion and a nickel-aluminum-semiconductor alloy drain portion.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: November 8, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ashish Baraskar, Raghuveer S. Makala, Peter Rabkin
  • Publication number: 20220352104
    Abstract: A bonded assembly of a first semiconductor die and a second semiconductor die includes first and second semiconductor dies. The first semiconductor die includes first semiconductor devices, first metal interconnect structures embedded in first dielectric material layers, and first metal bonding pads laterally surrounded by a semiconductor material layer. The second semiconductor die includes second semiconductor devices, second metal interconnect structures embedded in second dielectric material layers, and second metal bonding pads that include primary metal bonding pads and auxiliary metal bonding pads. The auxiliary metal bonding pads are bonded to the semiconductor material layer through metal-semiconductor compound portions formed by reaction of surface portions of the semiconductor material layer and an auxiliary metal bonding pad. The primary metal bonding pads are bonded to the first metal bonding pads by metal-to-metal bonding.
    Type: Application
    Filed: April 29, 2021
    Publication date: November 3, 2022
    Inventors: Lin HOU, Peter RABKIN, Masaaki HIGASHITANI
  • Patent number: 11476272
    Abstract: Memory stack structures extending through an alternating stack of insulating layers and electrically conductive layers is formed over a substrate. Each memory stack structure includes a memory film and a vertical semiconductor channel. A sacrificial polycrystalline metal layer may be formed on each memory film, and a carbon precursor may be decomposed on a physically exposed surface of the sacrificial polycrystalline metal layer to generate adsorbed carbon atoms. A subset of the adsorbed carbon atoms diffuses through grain boundaries in the polycrystalline e metal layer to an interface with the memory film. The carbon atoms at the interface may be coalesced into at least one graphene layer by an anneal process. The at least one graphene layer functions as a vertical semiconductor channel, which provides a higher mobility than silicon. A metallic drain region may be formed at an upper end of each vertical semiconductor channel.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: October 18, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Peter Rabkin, Masaaki Higashitani
  • Publication number: 20220310655
    Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located within the memory opening. The memory opening fill structure includes a gate dielectric and a ferroelectric semiconductor channel layer that is laterally spaced from the electrically conductive layers by the gate dielectric.
    Type: Application
    Filed: March 29, 2021
    Publication date: September 29, 2022
    Inventors: Peter RABKIN, Masaaki HIGASHITANI
  • Publication number: 20220310656
    Abstract: A memory device includes a ferroelectric semiconductor channel, a source region contacting a first portion of the ferroelectric semiconductor channel, a drain region located above the source region and contacting a second portion of the ferroelectric semiconductor channel located above the first portion, a word line, and a gate dielectric located between the word line and the ferroelectric semiconductor channel.
    Type: Application
    Filed: July 13, 2021
    Publication date: September 29, 2022
    Inventors: Peter RABKIN, Masaaki HIGASHITANI
  • Patent number: 11444016
    Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: September 13, 2022
    Assignee: SanDisk Technologes LLC
    Inventors: Luisa Lin, Mohan Dunga, Venkatesh P. Ramachandra, Peter Rabkin, Masaaki Higashitani