Abstract: Data processing circuitry comprises instruction queue circuitry to maintain one or more instruction queues to store fetched instructions; instruction decode circuitry to decode instructions dispatched from the one or more instruction queues, the instruction decode circuitry being configured to allocate one or more processor resources of a set of processor resources to a decoded instruction for use in execution of that decoded instruction; detection circuitry to detect, for an instruction to be dispatched from a given instruction queue, a prediction indicating whether sufficient processor resources are predicted to be available for allocation to that instruction by the instruction decode circuitry; and dispatch circuitry to dispatch an instruction from the given instruction queue to the instruction decode circuitry, the dispatch circuitry being responsive to the detection circuitry to allow deletion of the dispatched instruction from that instruction queue when the prediction indicates that sufficient processo

Abstract: A bullpup stock assembly configured for housing a firearm assembly without the use of tools. The bullpup stock includes an upper housing configured to hingedly couple with a lower housing. A hinging means hingedly couples the upper and lower housings such that in a closed configuration the forward ends upper and lower housing are joined, and such that in an open configuration the upper and lower housing are not joined. A bullpup trigger is configured to communicate with a trigger of the firearm assembly by a trigger linkage assembly such that the bullpup trigger activates the firearm when depressed. A block assembly housed with the upper and lower housings is configured to house a firing assembly of the firearm and the trigger linkage assembly. At least one locking means for locking the upper and lower housings together when the forward ends of the upper and lower housing are joined.

Abstract: An entitlement card can be assigned a product key real-time to provide a custom order of benefits including product and/or service, amount, and time. A method facilitating product key assignment for an entitlement can include receiving a request for activating a custom entitlement product key from, for example, a point of purchase. The request includes a request for particular benefits to a redeemer, including the particular product and/or service to be provided and the quantity and time period for the product and/or service. The method further includes assigning the benefits to the product key at the time of the request and activating the product key, which may be later redeemed for the assigned benefits.

Abstract: A system and method monitors for fraudulent transactions relating to a mobile device. Either of first and second processing nodes places a hold on a transaction associated with the first live-data flow and the second live-data flow responsive to detection of a potentially fraudulent condition. A third processing node generates an interactive verification communication responsive to the first data associated with the first live-data flow and the second data associated with the second live-data flow to establish a validity of the transaction. The third processing node releases the hold on the transaction responsive to the interactive verification communication determining the potentially fraudulent condition relates to a non-fraudulent transaction and generates a fraud detection response responsive to the interactive verification communication determining the potentially fraudulent condition relates to a fraudulent transaction before the transaction completes.

Abstract: A method for detecting and intercepting at least one of fraud, security breach, intrusion or misuse of network resources monitors at least one of a plurality of simultaneous live data flows that are in active transmission between a first endpoint and a second endpoint in a network prior to the storage of data within the live data flows in a database, to take action to control the operation of a network. Prescribed detection algorithms are updated for detecting prescribed patterns and deduced detection algorithms are updated for detecting deduced patterns within the plurality of simultaneous live data flows with at least one of live data conditions and external data sources. The deduced and prescribed patterns that indicate occurrence of at least one of fraud, security breach, intrusion or misuse of the network are detected from at least one of the live data flows and the external data sources using the prescribed detection algorithms and the deduced detection algorithms.

Abstract: A system for monitoring live-data flow through a network includes a processor implementing a first processing node including an ingestor virtual machine (ingestor VM) for monitoring a mirrored live-data flow of the live-data flow passing through a selected point within the network in a non-intrusive manner that does not affect the live-data flow of at least one live data flow passing through the selected point. The ingestor VM further decodes each packet within the mirrored data flow according to each protocol associated with a packet and manages processes occurring within and between the first processing node and a second processing node. A time dependent buffer virtual machine (TDB VM) allocates a time dependent buffer (TDB) within the memory for executing the processes performed within and between the first processing node and a second processing node, and releasing the allocated TDB after completion of the processes.

Abstract: A system and method monitors for fraudulent transactions relating to a mobile device. Either of first and second processing nodes places a hold on a transaction associated with the first live-data flow and the second live-data flow responsive to detection of a potentially fraudulent condition. A third processing node generates an interactive verification communication responsive to the first data associated with the first live-data flow and the second data associated with the second live-data flow to establish a validity of the transaction. The third processing node releases the hold on the transaction responsive to the interactive verification communication determining the potentially fraudulent condition relates to a non-fraudulent transaction and generates a fraud detection response responsive to the interactive verification communication determining the potentially fraudulent condition relates to a fraudulent transaction before the transaction completes.

Abstract: A passive intermodulation detection system is provided to remotely identify passive intermodulation at a base station site and diagnose the type of intermodulation and location of the non-linearity that is the source of the passive intermodulation. The passive intermodulation detection system can generate a test signal in a first band that is transmitted by an antenna. Another antenna can receive a signal in another band, and the passive intermodulation detection system can analysis the received signal to determine whether an intermodulation product due to a non-linearity is present. Based on the type of intermodulation product, period, order, frequency, and etc., the type and location of the non-linearity can be identified.

Abstract: A radiation beam, for example a therapeutic radiation beam such as an IMRT or VMAT X-ray beam is monitored using a Monolithic Active Pixel Sensor (MAPS) detector. Photons of the radiation beam can interact with the MAPS detector, and the radiation beam configuration can be estimated from the determined positions of the interactions. The detector is made sufficiently thin that it interacts only very weakly with the X-ray photons. For example, less than 1 in 103 of the X-ray photons might interact with the detector. Hence, the disturbance to the X-ray beam is negligible.

Abstract: An apparatus comprises a processing pipeline comprising out-of-order execution circuitry and second execution circuitry. Control circuitry monitors at least one reordering metric indicative of an extent to which instructions are executed out of order by the out-of-order execution circuitry, and controls whether instructions are executed using the out-of-order execution circuitry or the second execution circuitry based on the reordering metric. A speculation metric indicative of a fraction of executed instructions that are flushed due to a mis-speculation can also be used to determine whether to execute instructions on first or second execution circuitry having different performance or energy consumption characteristics.

Abstract: A data processing apparatus 2 performs multi-threaded processing using the processing pipeline 6, 8, 10, 12, 14, 16, 18. Flush control circuitry 30 is responsive to multiple different types of flush trigger. Different types of flush trigger result in different sets of state being flushed for the thread which resulted in the flush trigger with state for other thread not being flushed. For example, a relatively low latency stall may result in flushing back to a first flush point whereas a longer latency stall results in flushing back to a second flush point and the loss of more state data. The data flushed back to the first flushed point may be a subset of the data flushed back to the second flush point.

Abstract: Apparatus for processing data 2 is provided with fetch circuitry 16 for fetching program instructions for execution from one or more active threads of instructions having respective program counter values. Pipeline circuitry 22, 24 has a first operating mode and a second operating mode. Mode switching circuitry 30 switches the pipeline circuitry 22, 24, between the first operating mode and the second operating mode in dependence upon a number of active threads of program instructions having program instructions available to be executed. The first operating mode has a lower average energy consumption per instruction executed than the second operating mode and the second operating mode has a higher average rate of instruction execution for a single thread than the first operating mode. The first operating mode may utilise a barrel processing pipeline 22 to perform interleaved multiple thread processing.

Abstract: A processing pipeline may have first and second execution circuits having different performance or energy consumption characteristics. Instruction supply circuitry may support different instruction supply schemes with different energy consumption or performance characteristics. This can allow a further trade-off between performance and energy efficiency. Architectural state storage can be shared between the execute units to reduce the overhead of switching between the units. In a parallel execution mode, groups of instructions can be executed on both execute units in parallel.

Abstract: This invention is a digital signal processor capable of performing correlation of data with pseudo noise for code division multiple access (CDMA) decoding using clusters. Each cluster includes plural multipliers. The multipliers multiply real and imaginary parts of packed data by corresponding pseudo noise data. Within a cluster the real parts and the imaginary parts of the products are summed separately. This forms plural complex number outputs equal in number to the number of clusters. The pseudo noise data is offset relative to the data input differing amounts for different clusters. The clusters are divided into first half clusters receiving data from even numbered slots and second half clusters receiving data from odd numbered slots. The correlation unit includes a mask input to selectively zero a multiplier product.

Abstract: A sequence of buffered instructions includes branch instructions. Branch prediction circuitry predicts if each branch instruction will result in a taken branch when executed. Normally, the fetch circuitry retrieves speculative instructions between the time that a source branch instruction is retrieved and the prediction if that source branch instruction will result in the taken branch. If the source branch instruction is predicted as taken, then the speculative instructions are discarded, and a count value indicates a number of instructions in the sequence between that source branch instruction and a subsequent branch instruction in the sequence that is also predicted as taken. Responsive to a subsequent occurrence of the source branch instruction predicted as taken, a throttled mode limits the number of instructions subsequently retrieved dependent on the count value, and then any further instructions are not retrieved for a number of clock cycles.

Abstract: A system for monitoring live-data flow through a network includes a processor implementing a first processing node including an ingestor virtual machine (ingestor VM) for monitoring a mirrored live-data flow of the live-data flow passing through a selected point within the network in a non-intrusive manner that does not affect the live-data flow of at least one live data flow passing through the selected point. The ingestor VM further decodes each packet within the mirrored data flow according to each protocol associated with a packet and manages processes occurring within and between the first processing node and a second processing node. A time dependent buffer virtual machine (TDB VM) allocates a time dependent buffer (TDB) within the memory for executing the processes performed within and between the first processing node and a second processing node, and releasing the allocated TDB after completion of the processes.