Patents by Inventor Peter Slota, Jr.
Peter Slota, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11049819Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.Type: GrantFiled: November 15, 2019Date of Patent: June 29, 2021Assignee: International Business Machines CorporationInventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
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Patent number: 10685919Abstract: A laminate structure includes a conductive layer and a dielectric layer in contact with the conductive layer, the dielectric layer comprises a selectively patterned high-modulus dielectric material that balances a differential stress between the conductive layer and the dielectric layer to mechanically stiffen the laminate structure and reduce warpage.Type: GrantFiled: February 7, 2017Date of Patent: June 16, 2020Assignee: International Business Machines CorporationInventors: Mark C. Lamorey, Shidong Li, Janak G. Patel, Douglas O. Powell, David J. Russell, Peter Slota, Jr., David B. Stone
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Publication number: 20200083177Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.Type: ApplicationFiled: November 15, 2019Publication date: March 12, 2020Inventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
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Patent number: 10553544Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.Type: GrantFiled: October 27, 2017Date of Patent: February 4, 2020Assignee: International Business Machines CorporationInventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
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Patent number: 9935058Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.Type: GrantFiled: November 21, 2016Date of Patent: April 3, 2018Assignee: International Business Machines CorporationInventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
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Publication number: 20180068957Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.Type: ApplicationFiled: October 27, 2017Publication date: March 8, 2018Inventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, JR., David B. Stone
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Publication number: 20170148749Abstract: A laminate structure includes a conductive layer and a dielectric layer in contact with the conductive layer, the dielectric layer comprises a selectively patterned high-modulus dielectric material that balances a differential stress between the conductive layer and the dielectric layer to mechanically stiffen the laminate structure and reduce warpage.Type: ApplicationFiled: February 7, 2017Publication date: May 25, 2017Inventors: Mark C. Lamorey, Shidong Li, Janak G. Patel, Douglas O. Powell, David J. Russell, Peter Slota, JR., David B. Stone
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Publication number: 20170125358Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.Type: ApplicationFiled: November 21, 2016Publication date: May 4, 2017Inventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, JR., David B. Stone
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Patent number: 9613915Abstract: A laminate structure includes a conductive layer and a dielectric layer in contact with the conductive layer, the dielectric layer comprises a selectively patterned high-modulus dielectric material that balances a differential stress between the conductive layer and the dielectric layer to mechanically stiffen the laminate structure and reduce warpage.Type: GrantFiled: December 2, 2014Date of Patent: April 4, 2017Assignee: International Business Machines CorporationInventors: Mark C. Lamorey, Shidong Li, Janak G. Patel, Douglas O. Powell, David J. Russell, Peter Slota, Jr., David B. Stone
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Patent number: 9599664Abstract: Detection circuits, methods of use and manufacture and design structures are provided herein. The structure includes at least one signal line traversing one or more metal layers of an integrated circuit. Circuitry is coupled to the at least one signal line, which is structured to receive a signal with a known signal from the at least one signal line or a signal from a different potential and, based on which signal is received, determine whether there is a structural defect in the integrated circuit.Type: GrantFiled: May 15, 2015Date of Patent: March 21, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Luke D. Lacroix, Mark C. H. Lamorey, Steven F. Oakland, Janak G. Patel, Kerry P. Pfarr, Peter Slota, Jr., David B. Stone
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Patent number: 9543255Abstract: A laminate structure includes a conductive layer and a dielectric layer in contact with the conductive layer, the dielectric layer comprises a selectively patterned high-modulus dielectric material that balances a differential stress between the conductive layer and the dielectric layer to mechanically stiffen the laminate structure and reduce warpage.Type: GrantFiled: February 15, 2016Date of Patent: January 10, 2017Assignee: International Business Machines CorporationInventors: Mark C. Lamorey, Shidong Li, Janak G. Patel, Douglas O. Powell, David J. Russell, Peter Slota, Jr., David B. Stone
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Patent number: 9531209Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.Type: GrantFiled: August 10, 2015Date of Patent: December 27, 2016Assignee: International Business Machines CorporationInventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
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Publication number: 20160155708Abstract: A laminate structure includes a conductive layer and a dielectric layer in contact with the conductive layer, the dielectric layer comprises a selectively patterned high-modulus dielectric material that balances a differential stress between the conductive layer and the dielectric layer to mechanically stiffen the laminate structure and reduce warpage.Type: ApplicationFiled: December 2, 2014Publication date: June 2, 2016Inventors: Mark C. Lamorey, Shidong Li, Janak G. Patel, Douglas O. Powell, David J. Russell, Peter Slota, JR., David B. Stone
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Publication number: 20160157357Abstract: A laminate structure includes a conductive layer and a dielectric layer in contact with the conductive layer, the dielectric layer comprises a selectively patterned high-modulus dielectric material that balances a differential stress between the conductive layer and the dielectric layer to mechanically stiffen the laminate structure and reduce warpage.Type: ApplicationFiled: February 15, 2016Publication date: June 2, 2016Inventors: Mark C. Lamorey, Shidong Li, Janak G. Patel, Douglas O. Powell, David J. Russell, Peter Slota, JR., David B. Stone
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Patent number: 9252101Abstract: Packages for a three-dimensional die stack, methods for fabricating a package for a three-dimensional die stack, and methods for distributing power in a package for a three-dimensional die stack. The package may include a first lid, a second lid, a die stack located between the first lid and the second lid, a first thermal interface material layer between the first lid and a first die of the die stack, and a second thermal interface material layer between the second lid and the second die of the die stack. The second thermal interface material layer is comprised of a thermal interface material having a high electrical conductivity and a high thermal conductivity.Type: GrantFiled: April 2, 2015Date of Patent: February 2, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
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Patent number: 9245854Abstract: Apparatus and methods for an electronic package incorporating shielding against emissions of electromagnetic interference (EMI). According to an integrated circuit structure, a substrate is on a printed circuit board. An integrated circuit chip is on the substrate. The integrated circuit chip is electrically connected to the substrate. An EMI shielding unit is on the integrated circuit chip and the substrate. The EMI shielding unit comprises a lid covering the integrated circuit chip and portions of the substrate outside the integrated circuit chip. A fill material can be deposited within a cavity formed between the lid and the substrate. The fill material comprises an EMI absorbing material. A periphery of the lid comprises a side skirt, the side skirt circumscribing the integrated circuit chip and the substrate. EMI absorbing material is on the printed circuit board, and a portion of the side skirt is embedded in the EMI absorbing material.Type: GrantFiled: October 16, 2014Date of Patent: January 26, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: William L. Brodsky, Timothy W. Budell, Samuel R. Connor, Mark Curtis Hayes Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
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Patent number: 9209141Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.Type: GrantFiled: February 26, 2014Date of Patent: December 8, 2015Assignee: International Business Machines CorporationInventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
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Publication number: 20150349565Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.Type: ApplicationFiled: August 10, 2015Publication date: December 3, 2015Inventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, JR., David B. Stone
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Patent number: 9190399Abstract: Embodiments of the present invention disclose a semiconductor structure and method for increasing thermal dissipation in a three-dimensional integrated circuit package. In certain embodiments, the semiconductor structure comprises a logic die or a processor die attached to a substrate; a memory die stack attached to the logic die or the processor die; and a first lid attached to a first side of the logic or the processor die. The semiconductor structure further comprises a second lid attached to a second side of the memory die stack; a first heat sink attached to the first lid; and a second heat sink attached to the second lid.Type: GrantFiled: March 6, 2014Date of Patent: November 17, 2015Assignee: International Business Machines CorporationInventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
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Patent number: 9185807Abstract: Various embodiments include integrated circuit structures having an off-axis in-hole capacitor. In some embodiments, an integrated circuit (IC) structure includes: a substrate layer having an upper surface; an IC chip at least partially contained within the substrate layer and aligned with a minor axis perpendicular to the upper surface of the substrate layer; an aperture in the substrate layer, the aperture physically separated from the IC chip; and a capacitor in the aperture and at least partially contained within the substrate layer, the capacitor being physically isolated from the IC chip, wherein the capacitor is aligned with an axis perpendicular to the upper surface of the substrate layer and offset from the minor axis of the IC chip.Type: GrantFiled: May 11, 2015Date of Patent: November 10, 2015Assignee: GLOBALFOUNDRIES U.S. 2 LLCInventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone