Patents by Inventor Peter Slota, Jr.

Peter Slota, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130285251
    Abstract: An integrated circuit structure comprises a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator layers, and conductive via material within the via openings. The conductive via material within corresponding via openings of adjacent insulator layers are electrically connected to form continuous electrical via paths through the insulator layers between the top surface and the bottom surface of the laminated structure. Within each of the continuous electrical via paths, the via openings are positioned relative to each other to form a diagonal structural path of the conductive via material through the laminated structure. The corresponding via openings of the adjacent insulator layers partially overlap each other. The diagonal structural paths are non-perpendicular to the top surface and the bottom surface.
    Type: Application
    Filed: April 30, 2012
    Publication date: October 31, 2013
    Applicant: International Business Machines Corporation
    Inventors: Luke D. LaCroix, Mark C. H. Lamorey, Janak G. Patel, Peter Slota, JR., David B. Stone
  • Patent number: 8444043
    Abstract: An array of solder balls is attached to solder pads of one of a first substrate and a second substrate. After aligning the array of solder balls relative to solder pads of the other of the first substrate and the second substrate, a thermal-mass-increasing fixture is placed on a surface of the second substrate to form an assembly of the first substrate, the second substrate, and the array of the solder balls therebetween, and the thermal-mass-increasing fixture. The thermal-mass-increasing fixture is in physical contact with at least a surface of a periphery of the second substrate. The thermal-mass-increasing fixture reduces the cool-down rate of peripheral solder balls after a reflow step, thereby increasing time for deformation of peripheral solder balls during the cool-down and reducing the mechanical stress on the solder balls after the cool-down.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: William E. Bernier, Marcus E. Interrante, Rajneesh Kumar, Chenzhou Lian, Janak G. Patel, Peter Slota, Jr.
  • Publication number: 20120187953
    Abstract: Detection circuits, methods of use and manufacture and design structures are provided herein. The structure includes at least one signal line traversing one or more metal layers of an integrated circuit. Circuitry is coupled to the at least one signal line, which is structured to receive a signal with a known signal from the at least one signal line or a signal from a different potential and, based on which signal is received, determine whether there is a structural defect in the integrated circuit.
    Type: Application
    Filed: January 20, 2011
    Publication date: July 26, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Luke D. LACROIX, Mark C.H. Lamorey, Steven F. Oakland, Janak G. Patel, Kerry P. Pfarr, Peter Slota, JR., David B. Stone
  • Publication number: 20120074559
    Abstract: An integrated circuit package including a package substrate, a metal lid mounted to the package substrate, and a stack of two or more integrated circuit chips electrically connected to each other by through substrate vias. The stack of two or more integrated circuit chips is disposed within the metal lid and electrically mounted to the package substrate. An inner surface of a top of the metal lid is electrically connected to ground wires in the package substrate by the through substrate vias. The TSVs provide electromagnetic interference shielding. A conductive thermal interface material may also be used. An alternative embodiment includes a single integrated circuit chip using TSVs to ground the metal lid.
    Type: Application
    Filed: September 24, 2010
    Publication date: March 29, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy W. Budell, Mark C.H. Lamorey, Peter Slota, JR.
  • Publication number: 20120049874
    Abstract: A semiconductor test device including a plurality of conductive layers, each of the layers comprising integrated circuit devices, a plurality of insulating layers between the conductive layers, a plurality of heat generating structures positioned between the insulating layers and the conductive layers, each of the heat generating structures being sized and positioned to only heat a predetermined limited area of the plurality of layers, a plurality of thermal monitors positioned within each of the plurality of layers, a control unit operatively connected to the heat generating structures and the thermal monitors, the control unit individually cycling the heat generating structures on and off for multiple heat cycles, such that different areas of the layers are treated to different heat cycles.
    Type: Application
    Filed: August 25, 2010
    Publication date: March 1, 2012
    Applicant: International Business CorporationA
    Inventors: Luke D. LaCroix, Janak G. Patel, Peter Slota, JR., David B. Stone
  • Patent number: 4846929
    Abstract: Polyimide is etched by contacting the polyimide with an aqueous solution of a metal hydroxide followed by contact with an acid followed by contact with an aqueous solution of a metal hydroxide. Etching of chemically cured polyimide can be enhanced by employing a presoaking in hot water. Also, partially etched chemically cured polyimide is removed with a concentrated acid solution.In preparing a metal coated polyimide structure for subsequent gold plating, two flash etching steps with the polyimide etch between are employed after developing the photoresist.
    Type: Grant
    Filed: July 13, 1988
    Date of Patent: July 11, 1989
    Assignee: IBM Corporation
    Inventors: Steven L. Bard, Claudius Feger, John J. Glenning, Gareth G. Hougham, Steven E. Molis, Walter P. Pawlowski, John J. Ritsko, Peter Slota, Jr., Randy W. Snyder
  • Patent number: 4615763
    Abstract: The surface of a substrate is roughened by providing a substrate which comprises a resinous material and an inorganic particulate material; and etching a surface of the substrate to selectively etch the resinous material and thereby produce the roughened surface.
    Type: Grant
    Filed: January 2, 1985
    Date of Patent: October 7, 1986
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey D. Gelorme, William H. Lawrence, Peter Slota, Jr.