Abstract: Embodiments of the present invention disclose a semiconductor structure and method for increasing thermal dissipation in a three-dimensional integrated circuit package. In certain embodiments, the semiconductor structure comprises a logic die or a processor die attached to a substrate; a memory die stack attached to the logic die or the processor die; and a first lid attached to a first side of the logic or the processor die. The semiconductor structure further comprises a second lid attached to a second side of the memory die stack; a first heat sink attached to the first lid; and a second heat sink attached to the second lid.

Abstract: Detection circuits, methods of use and manufacture and design structures are provided herein. The structure includes at least one signal line traversing one or more metal layers of an integrated circuit. Circuitry is coupled to the at least one signal line, which is structured to receive a signal with a known signal from the at least one signal line or a signal from a different potential and, based on which signal is received, determine whether there is a structural defect in the integrated circuit.

Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

Abstract: Various embodiments include integrated circuit structures having an off-axis in-hole capacitor. In some embodiments, an integrated circuit (IC) structure includes: a substrate layer having an upper surface; an IC chip at least partially contained within the substrate layer and aligned with a minor axis perpendicular to the upper surface of the substrate layer; an aperture in the substrate layer, the aperture physically separated from the IC chip; and a capacitor in the aperture and at least partially contained within the substrate layer, the capacitor being physically isolated from the IC chip, wherein the capacitor is aligned with an axis perpendicular to the upper surface of the substrate layer and offset from the minor axis of the IC chip.

Abstract: Packages for a three-dimensional die stack, methods for fabricating a package for a three-dimensional die stack, and methods for distributing power in a package for a three-dimensional die stack. The package may include a first lid, a second lid, a die stack located between the first lid and the second lid, a first thermal interface material layer between the first lid and a first die of the die stack, and a second thermal interface material layer between the second lid and the second die of the die stack. The second thermal interface material layer is comprised of a thermal interface material having a high electrical conductivity and a high thermal conductivity.

Abstract: Packages for a three-dimensional die stack, methods for fabricating a package for a three-dimensional die stack, and methods for distributing power in a package for a three-dimensional die stack. The package may include a first lid, a second lid, a die stack located between the first lid and the second lid, a first thermal interface material layer between the first lid and a first die of the die stack, and a second thermal interface material layer between the second lid and the second die of the die stack. The second thermal interface material layer is comprised of a thermal interface material having a high electrical conductivity and a high thermal conductivity.

Abstract: Various embodiments include integrated circuit structures having an off-axis in-hole capacitor. In some embodiments, an integrated circuit (IC) structure includes: a substrate layer having an upper surface; an IC chip at least partially contained within the substrate layer and aligned with a minor axis perpendicular to the upper surface of the substrate layer; an aperture in the substrate layer, the aperture physically separated from the IC chip; and a capacitor in the aperture and at least partially contained within the substrate layer, the capacitor being physically isolated from the IC chip, wherein the capacitor is aligned with an axis perpendicular to the upper surface of the substrate layer and offset from the minor axis of the IC chip.

Abstract: Various embodiments include integrated circuit structures having an off-axis in-hole capacitor. In some embodiments, an integrated circuit (IC) structure includes: a substrate layer having an upper surface; an IC chip at least partially contained within the substrate layer and aligned with a minor axis perpendicular to the upper surface of the substrate layer; an aperture in the substrate layer, the aperture physically separated from the IC chip; and a capacitor in the aperture and at least partially contained within the substrate layer, the capacitor being physically isolated from the IC chip, wherein the capacitor is aligned with an axis perpendicular to the upper surface of the substrate layer and offset from the minor axis of the IC chip.

Abstract: Packages for a three-dimensional die stack, methods for fabricating a package for a three-dimensional die stack, and methods for distributing power in a package for a three-dimensional die stack. The package may include a first lid, a second lid, a die stack located between the first lid and the second lid, a first thermal interface material layer between the first lid and a first die of the die stack, and a second thermal interface material layer between the second lid and the second die of the die stack. The second thermal interface material layer is comprised of a thermal interface material having a high electrical conductivity and a high thermal conductivity.

Abstract: Detection circuits, methods of use and manufacture and design structures are provided herein. The structure includes at least one signal line traversing one or more metal layers of an integrated circuit. Circuitry is coupled to the at least one signal line, which is structured to receive a signal with a known signal from the at least one signal line or a signal from a different potential and, based on which signal is received, determine whether there is a structural defect in the integrated circuit.

Abstract: A method including a printed circuit board electrically coupled to a bottom of a laminate substrate, the laminate substrate having an opening extending through the entire thickness of the laminate substrate, a main die electrically coupled to a top of the laminate substrate, a die stack electrically coupled to a bottom of the main die, the die stack including one or more chips stacked vertically and electrically coupled to one another, the die stack extending into the opening of the laminate substrate, and an interposer positioned between and electrically coupled to a topmost chip and the printed circuit board, the interposer providing an electrical path from the printed circuit board to the topmost chip of the die stack.

Abstract: An integrated circuit structure includes a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator layers, and conductive via material within the via openings. The conductive via material within corresponding via openings of adjacent insulator layers are electrically connected to form continuous electrical via paths through the insulator layers between the top surface and the bottom surface of the laminated structure. Within each of the continuous electrical via paths, the via openings are positioned relative to each other to form a diagonal structural path of the conductive via material through the laminated structure. The corresponding via openings of the adjacent insulator layers partially overlap each other. The diagonal structural paths are non-perpendicular to the top surface and the bottom surface.

Abstract: A method including a printed circuit board electrically coupled to a bottom of a laminate substrate, the laminate substrate having an opening extending through the entire thickness of the laminate substrate, a main die electrically coupled to a top of the laminate substrate, a die stack electrically coupled to a bottom of the main die, the die stack including one or more chips stacked vertically and electrically coupled to one another, the die stack extending into the opening of the laminate substrate, and an interposer positioned between and electrically coupled to a topmost chip and the printed circuit board, the interposer providing an electrical path from the printed circuit board to the topmost chip of the die stack.

Abstract: Apparatus and methods for an electronic package incorporating shielding against emissions of electromagnetic interference (EMI). According to an integrated circuit structure, a substrate is on a printed circuit board. An integrated circuit chip is on the substrate. The integrated circuit chip is electrically connected to the substrate. An electromagnetic interference (EMI) shielding unit is on the integrated circuit chip and the substrate. The EMI shielding unit comprises a lid covering the integrated circuit chip and portions of the substrate outside the integrated circuit chip. A fill material can be deposited within a cavity formed between the lid and the substrate. The fill material comprises an EMI absorbing material. A periphery of the lid comprises a side skirt, the side skirt circumscribing the integrated circuit chip and the substrate. EMI absorbing material is on the printed circuit board, and a portion of the side skirt is embedded in the EMI absorbing material.

Abstract: Apparatus and methods for an electronic package incorporating shielding against emissions of electromagnetic interference (EMI). According to an integrated circuit structure, a substrate is on a printed circuit board. An integrated circuit chip is on the substrate. The integrated circuit chip is electrically connected to the substrate. An EMI shielding unit is on the integrated circuit chip and the substrate. The EMI shielding unit comprises a lid covering the integrated circuit chip and portions of the substrate outside the integrated circuit chip. A fill material can be deposited within a cavity formed between the lid and the substrate. The fill material comprises an EMI absorbing material. A periphery of the lid comprises a side skirt, the side skirt circumscribing the integrated circuit chip and the substrate. EMI absorbing material is on the printed circuit board, and a portion of the side skirt is embedded in the EMI absorbing material.

Abstract: An integrated circuit structure includes a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator layers, and conductive via material within the via openings. The conductive via material within corresponding via openings of adjacent insulator layers are electrically connected to form continuous electrical via paths through the insulator layers between the top surface and the bottom surface of the laminated structure. Within each of the continuous electrical via paths, the via openings are positioned relative to each other to form a diagonal structural path of the conductive via material through the laminated structure. The corresponding via openings of the adjacent insulator layers partially overlap each other. The diagonal structural paths are non-perpendicular to the top surface and the bottom surface.

Abstract: An integrated circuit structure includes a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator layers, and conductive via material within the via openings. The conductive via material within corresponding via openings of adjacent insulator layers are electrically connected to form continuous electrical via paths through the insulator layers between the top surface and the bottom surface of the laminated structure. Within each of the continuous electrical via paths, the via openings are positioned relative to each other to form a diagonal structural path of the conductive via material through the laminated structure. The corresponding via openings of the adjacent insulator layers partially overlap each other. The diagonal structural paths are non-perpendicular to the top surface and the bottom surface.

Abstract: A structure and method for monitoring interlevel dielectric stress damage. The structure includes a monitor solder bump and normal solder bumps; a set of stacked interlevel dielectric layers between the substrate and the monitor solder bump and the normal solder bumps, one or more ultra-low K dielectric layers comprising an ultra-low K material having a dielectric constant of 2.4 or less; a monitor structure in a region directly under the monitor solder bump in the ultra-low K dielectric layers and wherein the conductor density in at least one ultra-low K dielectric layer in the region directly under the monitor solder bumps is less than a specified minimum density and the conductor density in corresponding regions of the ultra-low K dielectric layers directly under normal solder bumps is greater than the specified minimum density.

Abstract: A semiconductor test device including a plurality of conductive layers, each of the layers comprising integrated circuit devices, a plurality of insulating layers between the conductive layers, a plurality of heat generating structures positioned between the insulating layers and the conductive layers, each of the heat generating structures being sized and positioned to only heat a predetermined limited area of the plurality of layers, a plurality of thermal monitors positioned within each of the plurality of layers, a control unit operatively connected to the heat generating structures and the thermal monitors, the control unit individually cycling the heat generating structures on and off for multiple heat cycles, such that different areas of the layers are treated to different heat cycles.

Abstract: A structure and method for monitoring interlevel dielectric stress damage. The structure includes a monitor solder bump and normal solder bumps; a set of stacked interlevel dielectric layers between the substrate and the monitor solder bump and the normal solder bumps, one or more ultra-low K dielectric layers comprising an ultra-low K material having a dielectric constant of 2.4 or less; a monitor structure in a region directly under the monitor solder bump in the ultra-low K dielectric layers and wherein the conductor density in at least one ultra-low K dielectric layer in the region directly under the monitor solder bumps is less than a specified minimum density and the conductor density in corresponding regions of the ultra-low K dielectric layers directly under normal solder bumps is greater than the specified minimum density.