Patents by Inventor Peter Vlasenko
Peter Vlasenko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10199933Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.Type: GrantFiled: February 9, 2018Date of Patent: February 5, 2019Assignee: Conversant Intellectual Property Management Inc.Inventors: Peter Vlasenko, Huy Tuong Mai
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Publication number: 20180331620Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.Type: ApplicationFiled: February 9, 2018Publication date: November 15, 2018Inventors: Peter Vlasenko, Huy Tuong Mai
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Patent number: 10122369Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.Type: GrantFiled: April 5, 2017Date of Patent: November 6, 2018Assignee: Conversant Intellectual Property Management Inc.Inventors: Peter Vlasenko, Dieter Haerle
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Patent number: 9917511Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.Type: GrantFiled: August 10, 2017Date of Patent: March 13, 2018Assignee: Conversant Intellectual Property Management Inc.Inventors: Peter Vlasenko, Huy Tuong Mai
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Publication number: 20180026529Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.Type: ApplicationFiled: August 10, 2017Publication date: January 25, 2018Inventors: Peter Vlasenko, Huy Tuong Mai
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Publication number: 20170272085Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.Type: ApplicationFiled: April 5, 2017Publication date: September 21, 2017Inventors: Peter Vlasenko, Dieter Haerle
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Patent number: 9762120Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.Type: GrantFiled: June 6, 2016Date of Patent: September 12, 2017Assignee: Conversant Intellectual Property Management Inc.Inventors: Peter Vlasenko, Huy Tuong Mai
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Publication number: 20160359408Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.Type: ApplicationFiled: June 6, 2016Publication date: December 8, 2016Inventors: Peter Vlasenko, Huy Tuong Mai
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Patent number: 9360878Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.Type: GrantFiled: October 13, 2014Date of Patent: June 7, 2016Assignee: Conversant Intellectual Property Management Inc.Inventors: Peter Vlasenko, Huy Tuong Mai
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Publication number: 20150028939Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.Type: ApplicationFiled: October 13, 2014Publication date: January 29, 2015Inventors: Peter Vlasenko, Huy Tuong Mai
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Patent number: 8860480Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.Type: GrantFiled: April 30, 2013Date of Patent: October 14, 2014Assignee: Conversant Intellectual Property Management Inc.Inventors: Peter Vlasenko, Huy Tuong Mai
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Publication number: 20140225651Abstract: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.Type: ApplicationFiled: April 21, 2014Publication date: August 14, 2014Applicant: Conversant Intellectual Property Management Inc.Inventors: Dieter Haerle, Tony Mai, Peter Vlasenko
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Patent number: 8704569Abstract: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.Type: GrantFiled: December 18, 2012Date of Patent: April 22, 2014Assignee: MOSAID Technologies IncorporatedInventors: Dieter Haerle, Tony Mai, Peter Vlasenko
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Publication number: 20140084977Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.Type: ApplicationFiled: November 27, 2013Publication date: March 27, 2014Applicant: MOSAID Technologies IncorporatedInventors: Peter Vlasenko, Dieter Haerle
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Patent number: 8599984Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.Type: GrantFiled: March 26, 2013Date of Patent: December 3, 2013Assignee: MOSAID Technologies IncorporatedInventors: Peter Vlasenko, Dieter Haerle
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Publication number: 20130234787Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.Type: ApplicationFiled: April 30, 2013Publication date: September 12, 2013Applicant: MOSAID Technologies, Inc.Inventors: Peter Vlasenko, Huy Tuong Mai
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Patent number: 8456208Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.Type: GrantFiled: February 27, 2012Date of Patent: June 4, 2013Assignee: Mosaid Technologies IncorporatedInventors: Peter Vlasenko, Huy Tuong Mai
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Patent number: 8411812Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.Type: GrantFiled: June 14, 2012Date of Patent: April 2, 2013Assignee: Mosaid Technologies IncorporatedInventors: Peter Vlasenko, Dieter Haerle
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Publication number: 20130003483Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.Type: ApplicationFiled: June 14, 2012Publication date: January 3, 2013Applicant: MOSAID Technologies IncorporatedInventors: Peter Vlasenko, Dieter Haerle
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Patent number: RE43947Abstract: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.Type: GrantFiled: May 11, 2011Date of Patent: January 29, 2013Assignee: Mosaid Technologies IncorporatedInventors: Dieter Haerle, Tony Mai, Peter Vlasenko