Abstract: A voltage level shifter with an input transistor pair, a cross-coupled load chain transistor pair and a pair of current sources, effects reduced power consumption through the use of the cross-coupled load chain transistor pair to minimize the DC current component present in known voltage level shifters. In specific embodiments, feedback elements may be used to minimize delays in signal transitions. A reference voltage that corresponds to a current capability of the input transistor pair may be used to regulate the current sources in the load chain. Changes in a swing of the input signal voltage received by the input transistor pair may be reflected in corresponding changes to the reference voltage. The voltage level shifter may be of particular use in a buffer.

Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.

Abstract: A power up circuit that having reduced power consumption during power saving modes, while maintaining an active flag signal indicating that the power supply voltage is satisfactory. This is achieved by turning off the power up circuit during the power saving mode, and using a status holding circuit to maintain the active flag signal in response to the power down signal. The status holding circuit is responsive to an internal node of the power up circuit for generating the active flag signal when the internal node has reached a predetermined level. The power down signal can be one or both a sleep mode signal and a deep power down signal. The status holding comprises an override circuit for maintaining the active flag signal in the power saving mode, and a restore circuit for rapidly resetting at least the internal node of the power up circuit upon exit of the power saving mode.

Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.

Abstract: An improved bias generator incorporates a reference voltage and/or a reference current into the generation of bias voltages. In some cases, the output of a biased delay element has a constant voltage swing. A delay line of such constant output voltage swing delay elements may be shown to provide reduced power consumption compared to some known self-biased delay lines. Furthermore, in other cases, providing the reference current to a novel bias generator allows a delay line of delay elements biased by such a novel bias generator to show reduced sensitivity to operating conditions, reduced sensitivity to variation in process parameters and improved signal quality, thereby providing more robust operation.

Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

Abstract: An improved bias generator incorporates a reference voltage and/or a reference current into the generation of bias voltages. In some cases, the output of a biased delay element has a constant voltage swing. A delay line of such constant output voltage swing delay elements may be shown to provide reduced power consumption compared to some known self-biased delay lines. Furthermore, in other cases, providing the reference current to a novel bias generator allows a delay line of delay elements biased by such a novel bias generator to show reduced sensitivity to operating conditions, reduced sensitivity to variation in process parameters and improved signal quality, thereby providing more robust operation.

Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.

Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

Abstract: An improved bias generator incorporates a reference voltage and/or a reference current into the generation of bias voltages. In some cases, the output of a biased delay element has a constant voltage swing. A delay line of such constant output voltage swing delay elements may be shown to provide reduced power consumption compared to some known self-biased delay lines. Furthermore, in other cases, providing the reference current to a novel bias generator allows a delay line of delay elements biased by such a novel bias generator to show reduced sensitivity to operating conditions, reduced sensitivity to variation in process parameters and improved signal quality, thereby providing more robust operation.

Abstract: A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump.

Abstract: A voltage level shifter with an input transistor pair, a cross-coupled load chain transistor pair and a pair of current sources, effects reduced power consumption through the use of the cross-coupled load chain transistor pair to minimize the DC current component present in known voltage level shifters. In specific embodiments, feedback elements may be used to minimize delays in signal transitions. A reference voltage that corresponds to a current capability of the input transistor pair may be used to regulate the current sources in the load chain. Changes in a swing of the input signal voltage received by the input transistor pair may be reflected in corresponding changes to the reference voltage. The voltage level shifter may be of particular use in a buffer.

Abstract: A voltage level shifter with an input transistor pair, a cross-coupled load chain transistor pair and a pair of current sources, effects reduced power consumption through the use of the cross-coupled load chain transistor pair to minimize the DC current component present in known voltage level shifters. In specific embodiments, feedback elements may be used to minimize delays in signal transitions. A reference voltage that corresponds to a current capability of the input transistor pair may be used to regulate the current sources in the load chain. Changes in a swing of the input signal voltage received by the input transistor pair may be reflected in corresponding changes to the reference voltage. The voltage level shifter may be of particular use in a buffer.

Abstract: An improved bias generator incorporates a reference voltage and/or a reference current into the generation of bias voltages. In some cases, the output of a biased delay element has a constant voltage swing. A delay line of such constant output voltage swing delay elements may be shown to provide reduced power consumption compared to some known self-biased delay lines. Furthermore, in other cases, providing the reference current to a novel bias generator allows a delay line of delay elements biased by such a novel bias generator to show reduced sensitivity to operating conditions, reduced sensitivity to variation in process parameters and improved signal quality, thereby providing more robust operation.

Abstract: A power up circuit that having reduced power consumption during power saving modes, while maintaining an active flag signal indicating that the power supply voltage is satisfactory. This is achieved by turning off the power up circuit during the power saving mode, and using a status holding circuit to maintain the active flag signal in response to the power down signal. The status holding circuit is responsive to an internal node of the power up circuit for generating the active flag signal when the internal node has reached a predetermined level. The power down signal can be one or both a sleep mode signal and a deep power down signal. The status holding comprises an override circuit for maintaining the active flag signal in the power saving mode, and a restore circuit for rapidly resetting at least the internal node of the power up circuit upon exit of the power saving mode.

Abstract: A power up circuit that having reduced power consumption during power saving modes, while maintaining an active flag signal indicating that the power supply voltage is satisfactory. This is achieved by turning off the power up circuit during the power saving mode, and using a status holding circuit to maintain the active flag signal in response to the power down signal. The status holding circuit is responsive to an internal node of the power up circuit for generating the active flag signal when the internal node has reached a predetermined level. The power down signal can be one or both a sleep mode signal and a deep power down signal. The status holding comprises an override circuit for maintaining the active flag signal in the power saving mode, and a restore circuit for rapidly resetting at least the internal node of the power up circuit upon exit of the power saving mode.

Abstract: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.

Abstract: An improved bias generator incorporates a reference voltage and/or a reference current into the generation of bias voltages. In some cases, the output of a biased delay element has a constant voltage swing. A delay line of such constant output voltage swing delay elements may be shown to provide reduced power consumption compared to some known self-biased delay lines. Furthermore, in other cases, careful selection of parameters for providing the reference voltage and/or providing the reference current to a novel bias generator allows a delay line of delay elements biased by such a novel bias generator to show reduced sensitivity to operating conditions, reduced sensitivity to variation in process parameters and improved signal quality, thereby providing more robust operation.

Abstract: A voltage level shifter with an input transistor pair, a cross-coupled load chain transistor pair and a pair of current sources, effects reduced power consumption through the use of the cross-coupled load chain transistor pair to minimize the DC current component present in known voltage level shifters. In specific embodiments, feedback elements may be used to minimize delays in signal transitions. A reference voltage that corresponds to a current capability of the input transistor pair may be used to regulate the current sources in the load chain. Changes in a swing of the input signal voltage received by the input transistor pair may be reflected in corresponding changes to the reference voltage. The voltage level shifter may be of particular use in a buffer.