Patents by Inventor Pezhman Monadgemi
Pezhman Monadgemi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230378137Abstract: A semiconductor device assembly comprises a substrate including internal contacts on a first side and first external contacts on a second side. The assembly further comprises one or more first dies disposed over the first side and electrically coupled to the internal contacts, and a interposer having a length and a width less than a length and a width of the substrate, having inner contacts on a first side, and having second external contacts on a second side. The interposer is coupled to the second side of the substrate by one or more of the inner contacts. The assembly further comprises a second die disposed between the substrate and the interposer. The assembly further comprises first solder balls on the first external contacts, and second solder balls on the second external contacts. The first and second solder balls are configured to bond with co-planar package contacts.Type: ApplicationFiled: August 7, 2023Publication date: November 23, 2023Inventor: Pezhman Monadgemi
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Patent number: 11742328Abstract: A semiconductor device assembly comprises a substrate including internal contacts on a first side and first external contacts on a second side. The assembly further comprises one or more first dies disposed over the first side and electrically coupled to the internal contacts, and a interposer having a length and a width less than a length and a width of the substrate, having inner contacts on a first side, and having second external contacts on a second side. The interposer is coupled to the second side of the substrate by one or more of the inner contacts. The assembly further comprises a second die disposed between the substrate and the interposer. The assembly further comprises first solder balls on the first external contacts, and second solder balls on the second external contacts. The first and second solder balls are configured to bond with co-planar package contacts.Type: GrantFiled: July 24, 2021Date of Patent: August 29, 2023Assignee: Micron Technology, Inc.Inventor: Pezhman Monadgemi
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Publication number: 20220208728Abstract: A semiconductor device assembly comprises a substrate including internal contacts on a first side and first external contacts on a second side. The assembly further comprises one or more first dies disposed over the first side and electrically coupled to the internal contacts, and a interposer having a length and a width less than a length and a width of the substrate, having inner contacts on a first side, and having second external contacts on a second side. The interposer is coupled to the second side of the substrate by one or more of the inner contacts. The assembly further comprises a second die disposed between the substrate and the interposer. The assembly further comprises first solder balls on the first external contacts, and second solder balls on the second external contacts. The first and second solder balls are configured to bond with co-planar package contacts.Type: ApplicationFiled: July 24, 2021Publication date: June 30, 2022Inventor: Pezhman Monadgemi
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Patent number: 10562766Abstract: Methods, compositions and arrays for non-random loading of single analyte molecules into array structures are provided. Arrays of confined regions are produced wherein each confined region comprises a single island within the confined region. The island can be selectively functionalized with a coupling agent to couple a single molecule of interest within the confined region.Type: GrantFiled: March 24, 2017Date of Patent: February 18, 2020Assignee: Pacific Biosciences of California, Inc.Inventors: Stephen Turner, Ron Kuse, Gregory Kearns, Pezhman Monadgemi, Mathieu Foquet, Drew Martinez
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Patent number: 10475733Abstract: An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer.Type: GrantFiled: October 10, 2018Date of Patent: November 12, 2019Assignee: Invensas CorporationInventors: Cyprian Emeka Uzoh, Pezhman Monadgemi, Terrence Caskey, Fatima Lina Ayatollahi, Belgacem Haba, Charles G. Woychik, Michael Newman
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Patent number: 10297582Abstract: A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds.Type: GrantFiled: November 25, 2015Date of Patent: May 21, 2019Assignee: Invensas CorporationInventors: Terrence Caskey, Ilyas Mohammed, Cyprian Emeka Uzoh, Charles G. Woychik, Michael Newman, Pezhman Monadgemi, Reynaldo Co, Ellis Chau, Belgacem Haba
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Publication number: 20190139878Abstract: An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer.Type: ApplicationFiled: October 10, 2018Publication date: May 9, 2019Inventors: Cyprian Emeka Uzoh, Pezhman Monadgemi, Terrence Caskey, Fatima Lina Ayatollahi, Belgacem Haba, Charles G. Woychik, Michael Newman
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Patent number: 10181411Abstract: An insulating second element is provided and overlies a surface of a first element which consists essentially of a material having a CTE of less than 10 ppm/° C. and has a first thickness in a first direction normal to the surface. Openings extend in the first direction through the second element. The first element is abraded to produce a thinned first element having a second thickness less than the first thickness. Conductive elements are formed at a first side of the interposer coincident with or adjacent to a surface of the thinned first element remote from the second element. A conductive structure extends through the openings in the second element, wherein the conductive elements are electrically connected with terminals of the interposer through the conductive structure, and the terminals are disposed at a second side of the interposer opposite from the first side.Type: GrantFiled: November 24, 2015Date of Patent: January 15, 2019Assignee: Invensas CorporationInventors: Michael Newman, Cyprian Uzoh, Charles G. Woychik, Pezhman Monadgemi, Terrence Caskey
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Patent number: 10103094Abstract: An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer.Type: GrantFiled: June 19, 2017Date of Patent: October 16, 2018Assignee: Invensas CorporationInventors: Cyprian Emeka Uzoh, Pezhman Monadgemi, Terrence Caskey, Fatima Lina Ayatollahi, Belgacem Haba, Charles G. Woychik, Michael Newman
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Publication number: 20170365546Abstract: An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer.Type: ApplicationFiled: June 19, 2017Publication date: December 21, 2017Applicant: Invensas CorporationInventors: Cyprian Emeka Uzoh, Pezhman Monadgemi, Terrence Caskey, Fatima Lina Ayatollahi, Belgacem Haba, Charles G. Woychik, Michael Newman
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Publication number: 20170253480Abstract: Methods, compositions and arrays for non-random loading of single analyte molecules into array structures are provided. Arrays of confined regions are produced wherein each confined region comprises a single island within the confined region. The island can be selectively functionalized with a coupling agent to couple a single molecule of interest within the confined region.Type: ApplicationFiled: March 24, 2017Publication date: September 7, 2017Inventors: Stephen Turner, Ron Kuse, Gregory Kearns, Pezhman Monadgemi, Mathieu Foquet, Drew Martinez
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Patent number: 9689800Abstract: Processes for making high multiplex arrays for use in analyzing discrete reactions at ultra high multiplex with reduced optical noise, and increased system flexibility. The high multiplex arrays include substrates having integrated optical components that increase multiplex capability by one or more of increasing density of reaction regions, improving transmission of light to or collection of light from discrete reactions regions. Integrated optical components include reflective optical elements which re-direct illumination light and light emitted from the discrete regions to more efficiently collect emitted light. Particularly preferred applications include single molecule reaction analysis, such as polymerase mediated template dependent nucleic acid synthesis and sequence determination.Type: GrantFiled: August 27, 2014Date of Patent: June 27, 2017Assignee: Pacific Biosciences of California, Inc.Inventors: Denis Zaccarin, Stephen Turner, Pezhman Monadgemi, Ravi Saxena
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Patent number: 9685401Abstract: An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer.Type: GrantFiled: July 31, 2015Date of Patent: June 20, 2017Assignee: Invensas CorporationInventors: Cyprian Emeka Uzoh, Pezhman Monadgemi, Terrence Caskey, Fatima Lina Ayatollahi, Belgacem Haba, Charles G. Woychik, Michael Newman
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Patent number: 9637380Abstract: Methods, compositions and arrays for non-random loading of single analyte molecules into array structures are provided. Arrays of confined regions are produced wherein each confined region comprises a single island within the confined region. The island can be selectively functionalized with a coupling agent to couple a single molecule of interest within the confined region.Type: GrantFiled: April 27, 2011Date of Patent: May 2, 2017Assignee: Pacific Biosciences of California, Inc.Inventors: Stephen Turner, Ron Kuse, Gregory Kearns, Pezhman Monadgemi, Mathieu Foquet, Drew Martinez
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Patent number: 9601398Abstract: A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate.Type: GrantFiled: September 29, 2014Date of Patent: March 21, 2017Assignee: Invensas CorporationInventors: Charles G. Woychik, Se Young Yang, Pezhman Monadgemi, Terrence Caskey, Cyprian Emeka Uzoh
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Patent number: 9502390Abstract: A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds.Type: GrantFiled: March 12, 2013Date of Patent: November 22, 2016Assignee: Invensas CorporationInventors: Terrence Caskey, Ilyas Mohammed, Cyprian Emeka Uzoh, Charles G. Woychik, Michael Newman, Pezhman Monadgemi, Reynaldo Co, Ellis Chau, Belgacem Haba
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Patent number: 9379008Abstract: Structures and methods of forming the same are disclosed herein. In one embodiment, a structure can comprise a region having first and second oppositely facing surfaces. A barrier region can overlie the region. An alloy region can overlie the barrier region. The alloy region can include a first metal and one or more elements selected from the group consisting of silicon (Si), germanium (Ge), indium (Id), boron (B), arsenic (As), antimony (Sb), tellurium (Te), or cadmium (Cd).Type: GrantFiled: February 20, 2015Date of Patent: June 28, 2016Assignee: Invensas CorporationInventors: Cyprian Emeka Uzoh, Charles G. Woychik, Michael Newman, Pezhman Monadgemi, Terrence Caskey
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Publication number: 20160176706Abstract: Systems and methods for forming MEMS assemblies incorporating getters are described. One such method for forming and bonding to a microelectromechanical systems (MEMS) assembly includes providing a first MEMS wafer including a metal layer on an inner surface and one or more cavities for forming a MEMS component, attaching a MEMS capping wafer, having at least one through hole via, to the inner surface of the first MEMS wafer thereby forming at least one encapsulated MEMs component within the first MEMS wafer, and bonding a wire to the metal layer through an open end of the at least one through hole via.Type: ApplicationFiled: November 17, 2015Publication date: June 23, 2016Applicant: Western Digital (Fremont), LLCInventors: Pezhman Monadgemi, Lei Wang
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Publication number: 20160176705Abstract: Systems and methods for forming MEMS assemblies incorporating getters are described. One such method for forming and bonding to a microelectromechanical systems (MEMS) assembly includes providing a first MEMS wafer including a metal layer on an inner surface and one or more cavities for forming a MEMS component, attaching a MEMS capping wafer, having at least one through hole via, to the inner surface of the first MEMS wafer thereby forming at least one encapsulated MEMs component within the first MEMS wafer, and bonding a wire to the metal layer through an open end of the at least one through hole via.Type: ApplicationFiled: November 17, 2015Publication date: June 23, 2016Applicant: Western Digital (Fremont), LLCInventors: Pezhman Monadgemi, Lei Wang
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Patent number: 9355905Abstract: Methods of forming a microelectronic assembly and the resulting structures and devices are disclosed herein. In one embodiment, a method of forming a microelectronic assembly includes removing material exposed at portions of a surface of a substrate to form a processed substrate having a plurality of thinned portions separated by integral supporting portions of the processed substrate having a thickness greater than a thickness of the thinned portions, at least some of the thinned portions including a plurality of electrically conductive interconnects extending in a direction of the thicknesses of the thinned portions and exposed at the surface; and removing the supporting portions of the substrate to sever the substrate into a plurality of individual thinned portions, at least some individual thinned portions including the interconnects.Type: GrantFiled: May 27, 2015Date of Patent: May 31, 2016Assignee: Invensas CorporationInventors: Cyprian Emeka Uzoh, Pezhman Monadgemi, Michael Newman, Charles G. Woychik, Terrence Caskey