Patents by Inventor Pezhman Monadgemi

Pezhman Monadgemi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10562766
    Abstract: Methods, compositions and arrays for non-random loading of single analyte molecules into array structures are provided. Arrays of confined regions are produced wherein each confined region comprises a single island within the confined region. The island can be selectively functionalized with a coupling agent to couple a single molecule of interest within the confined region.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: February 18, 2020
    Assignee: Pacific Biosciences of California, Inc.
    Inventors: Stephen Turner, Ron Kuse, Gregory Kearns, Pezhman Monadgemi, Mathieu Foquet, Drew Martinez
  • Patent number: 10475733
    Abstract: An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: November 12, 2019
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Pezhman Monadgemi, Terrence Caskey, Fatima Lina Ayatollahi, Belgacem Haba, Charles G. Woychik, Michael Newman
  • Patent number: 10297582
    Abstract: A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: May 21, 2019
    Assignee: Invensas Corporation
    Inventors: Terrence Caskey, Ilyas Mohammed, Cyprian Emeka Uzoh, Charles G. Woychik, Michael Newman, Pezhman Monadgemi, Reynaldo Co, Ellis Chau, Belgacem Haba
  • Publication number: 20190139878
    Abstract: An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer.
    Type: Application
    Filed: October 10, 2018
    Publication date: May 9, 2019
    Inventors: Cyprian Emeka Uzoh, Pezhman Monadgemi, Terrence Caskey, Fatima Lina Ayatollahi, Belgacem Haba, Charles G. Woychik, Michael Newman
  • Patent number: 10181411
    Abstract: An insulating second element is provided and overlies a surface of a first element which consists essentially of a material having a CTE of less than 10 ppm/° C. and has a first thickness in a first direction normal to the surface. Openings extend in the first direction through the second element. The first element is abraded to produce a thinned first element having a second thickness less than the first thickness. Conductive elements are formed at a first side of the interposer coincident with or adjacent to a surface of the thinned first element remote from the second element. A conductive structure extends through the openings in the second element, wherein the conductive elements are electrically connected with terminals of the interposer through the conductive structure, and the terminals are disposed at a second side of the interposer opposite from the first side.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: January 15, 2019
    Assignee: Invensas Corporation
    Inventors: Michael Newman, Cyprian Uzoh, Charles G. Woychik, Pezhman Monadgemi, Terrence Caskey
  • Patent number: 10103094
    Abstract: An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: October 16, 2018
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Pezhman Monadgemi, Terrence Caskey, Fatima Lina Ayatollahi, Belgacem Haba, Charles G. Woychik, Michael Newman
  • Publication number: 20170365546
    Abstract: An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer.
    Type: Application
    Filed: June 19, 2017
    Publication date: December 21, 2017
    Applicant: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Pezhman Monadgemi, Terrence Caskey, Fatima Lina Ayatollahi, Belgacem Haba, Charles G. Woychik, Michael Newman
  • Publication number: 20170253480
    Abstract: Methods, compositions and arrays for non-random loading of single analyte molecules into array structures are provided. Arrays of confined regions are produced wherein each confined region comprises a single island within the confined region. The island can be selectively functionalized with a coupling agent to couple a single molecule of interest within the confined region.
    Type: Application
    Filed: March 24, 2017
    Publication date: September 7, 2017
    Inventors: Stephen Turner, Ron Kuse, Gregory Kearns, Pezhman Monadgemi, Mathieu Foquet, Drew Martinez
  • Patent number: 9689800
    Abstract: Processes for making high multiplex arrays for use in analyzing discrete reactions at ultra high multiplex with reduced optical noise, and increased system flexibility. The high multiplex arrays include substrates having integrated optical components that increase multiplex capability by one or more of increasing density of reaction regions, improving transmission of light to or collection of light from discrete reactions regions. Integrated optical components include reflective optical elements which re-direct illumination light and light emitted from the discrete regions to more efficiently collect emitted light. Particularly preferred applications include single molecule reaction analysis, such as polymerase mediated template dependent nucleic acid synthesis and sequence determination.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: June 27, 2017
    Assignee: Pacific Biosciences of California, Inc.
    Inventors: Denis Zaccarin, Stephen Turner, Pezhman Monadgemi, Ravi Saxena
  • Patent number: 9685401
    Abstract: An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: June 20, 2017
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Pezhman Monadgemi, Terrence Caskey, Fatima Lina Ayatollahi, Belgacem Haba, Charles G. Woychik, Michael Newman
  • Patent number: 9637380
    Abstract: Methods, compositions and arrays for non-random loading of single analyte molecules into array structures are provided. Arrays of confined regions are produced wherein each confined region comprises a single island within the confined region. The island can be selectively functionalized with a coupling agent to couple a single molecule of interest within the confined region.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: May 2, 2017
    Assignee: Pacific Biosciences of California, Inc.
    Inventors: Stephen Turner, Ron Kuse, Gregory Kearns, Pezhman Monadgemi, Mathieu Foquet, Drew Martinez
  • Patent number: 9601398
    Abstract: A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: March 21, 2017
    Assignee: Invensas Corporation
    Inventors: Charles G. Woychik, Se Young Yang, Pezhman Monadgemi, Terrence Caskey, Cyprian Emeka Uzoh
  • Patent number: 9502390
    Abstract: A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: November 22, 2016
    Assignee: Invensas Corporation
    Inventors: Terrence Caskey, Ilyas Mohammed, Cyprian Emeka Uzoh, Charles G. Woychik, Michael Newman, Pezhman Monadgemi, Reynaldo Co, Ellis Chau, Belgacem Haba
  • Patent number: 9379008
    Abstract: Structures and methods of forming the same are disclosed herein. In one embodiment, a structure can comprise a region having first and second oppositely facing surfaces. A barrier region can overlie the region. An alloy region can overlie the barrier region. The alloy region can include a first metal and one or more elements selected from the group consisting of silicon (Si), germanium (Ge), indium (Id), boron (B), arsenic (As), antimony (Sb), tellurium (Te), or cadmium (Cd).
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: June 28, 2016
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Charles G. Woychik, Michael Newman, Pezhman Monadgemi, Terrence Caskey
  • Publication number: 20160176706
    Abstract: Systems and methods for forming MEMS assemblies incorporating getters are described. One such method for forming and bonding to a microelectromechanical systems (MEMS) assembly includes providing a first MEMS wafer including a metal layer on an inner surface and one or more cavities for forming a MEMS component, attaching a MEMS capping wafer, having at least one through hole via, to the inner surface of the first MEMS wafer thereby forming at least one encapsulated MEMs component within the first MEMS wafer, and bonding a wire to the metal layer through an open end of the at least one through hole via.
    Type: Application
    Filed: November 17, 2015
    Publication date: June 23, 2016
    Applicant: Western Digital (Fremont), LLC
    Inventors: Pezhman Monadgemi, Lei Wang
  • Publication number: 20160176705
    Abstract: Systems and methods for forming MEMS assemblies incorporating getters are described. One such method for forming and bonding to a microelectromechanical systems (MEMS) assembly includes providing a first MEMS wafer including a metal layer on an inner surface and one or more cavities for forming a MEMS component, attaching a MEMS capping wafer, having at least one through hole via, to the inner surface of the first MEMS wafer thereby forming at least one encapsulated MEMs component within the first MEMS wafer, and bonding a wire to the metal layer through an open end of the at least one through hole via.
    Type: Application
    Filed: November 17, 2015
    Publication date: June 23, 2016
    Applicant: Western Digital (Fremont), LLC
    Inventors: Pezhman Monadgemi, Lei Wang
  • Patent number: 9355905
    Abstract: Methods of forming a microelectronic assembly and the resulting structures and devices are disclosed herein. In one embodiment, a method of forming a microelectronic assembly includes removing material exposed at portions of a surface of a substrate to form a processed substrate having a plurality of thinned portions separated by integral supporting portions of the processed substrate having a thickness greater than a thickness of the thinned portions, at least some of the thinned portions including a plurality of electrically conductive interconnects extending in a direction of the thicknesses of the thinned portions and exposed at the surface; and removing the supporting portions of the substrate to sever the substrate into a plurality of individual thinned portions, at least some individual thinned portions including the interconnects.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: May 31, 2016
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Pezhman Monadgemi, Michael Newman, Charles G. Woychik, Terrence Caskey
  • Patent number: 9323010
    Abstract: To fabricate an interposer for interfacing waveguides (e.g. optical fiber cables) to transducers, a cavity (410) is formed in a top surface of a substrate. A first layer (520) is formed over the cavity's bottom surface, with one or more gaps in the first layer's top surface. A second layer (3410) is formed in the one or more gaps. The second layer overlaps the first layer. At least part of the first layer is removed to form channels separated from each other by portions of the second layer that are located in the one or more gaps; at least part of the first layer is removed from under the second layer. The second layer portions in the one or more gaps provide one or more spacers in the cavity; these one or more spacers at least partially cover the channels. Waveguides can be placed into the channels.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: April 26, 2016
    Assignee: Invensas Corporation
    Inventors: Valentin Kosenko, Edward Lee McBain, Cyprian Emeka Uzoh, Pezhman Monadgemi, Sergey Savastiouk
  • Patent number: 9312175
    Abstract: Microelectronic elements and methods of their manufacture are disclosed. A microelectronic element may include a substrate including an opening extending through a semiconductor region of the substrate, a dielectric layer cover a wall of the opening within at least a first portion of the opening, a first metal disposed within the first portion of the opening, a second metal disposed within a second portion of the opening. The second metal may form at least part of a contact of the microelectronic element.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: April 12, 2016
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Fatima Lina Ayatollahi, Michael Newman, Pezhman Monadgemi
  • Publication number: 20160079090
    Abstract: An interposer has conductive elements at a first side and terminals at a second side opposite therefrom, for connecting with a microelectronic element and a second component, respectively. The component includes a first element having a thermal expansion coefficient less than 10 ppm/° C., and an insulating second element, with a plurality of openings extending from the second side through the second element towards the first element. A conductive structure extending through the openings in the second element and through the first element electrically connects the terminals with the conductive elements.
    Type: Application
    Filed: November 24, 2015
    Publication date: March 17, 2016
    Inventors: Michael Newman, Cyprian Uzoh, Charles G. Woychik, Pezhman Monadgemi, Terrence Caskey