Patents by Inventor Phil-Ouk Nam
Phil-Ouk Nam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11913114Abstract: A semiconductor manufacturing apparatus including a process chamber and a boat having a support member supporting substrates arranged in a first direction. An inner tube encloses the boat and includes a slit along a side wall. A nozzle supplies a process gas and includes a gas injection port at a position corresponding to the slit. The gas injection port includes a first inlet and first outlet. The slit includes a second inlet and second outlet. A distance to an end of the first inlet from a center line that connects a center of the first inlet and a center of the second outlet is different from the distance from the center line to an end of the first outlet and/or a distance from the center line to an end of the second inlet is different from a distance from the center line to an end of the second outlet.Type: GrantFiled: August 3, 2020Date of Patent: February 27, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae Hyun Yang, Sang Yub Ie, Tae Yong Kim, Phil Ouk Nam
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Patent number: 11910614Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.Type: GrantFiled: April 1, 2022Date of Patent: February 20, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang Sup Lee, Phil Ouk Nam, Sung Yun Lee, Chang Seok Kang
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Publication number: 20240018657Abstract: A semiconductor manufacturing apparatus including a process chamber and a boat having a support member supporting substrates arranged in a first direction. An inner tube encloses the boat and includes a slit along a side wall. A nozzle supplies a process gas and includes a gas injection port at a position corresponding to the slit. The gas injection port includes a first inlet and first outlet. The slit includes a second inlet and second outlet. A distance to an end of the first inlet from a center line that connects a center of the first inlet and a center of the second outlet is different from the distance from the center line to an end of the first outlet and/or a distance from the center line to an end of the second inlet is different from a distance from the center line to an end of the second outlet.Type: ApplicationFiled: September 27, 2023Publication date: January 18, 2024Inventors: Jae Hyun YANG, Sang Yub IE, Tae Yong KIM, Phil Ouk NAM
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Patent number: 11737277Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.Type: GrantFiled: November 10, 2021Date of Patent: August 22, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Hoon Choi, Sung Gil Kim, Seulye Kim, Jung Ho Kim, Hong Suk Kim, Phil Ouk Nam, Jae Young Ahn, Han Jin Lim
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Patent number: 11532639Abstract: Disclosed is a three-dimensional semiconductor memory device including a carbon-containing layer on a substrate, a plurality of electrode interlayer dielectric layers and a plurality of electrode layers that are alternately stacked on the carbon-containing layer, a cell vertical pattern that penetrates at least some of the electrode interlayer dielectric layers and the electrode layers, and a semiconductor pattern between the cell vertical pattern and the carbon-containing layer. The substrate includes a plurality of first grains. The semiconductor pattern includes a plurality of second grains. An average size of the second grains is less than an average size of the first grains.Type: GrantFiled: September 29, 2020Date of Patent: December 20, 2022Inventors: Sangsoo Lee, Chaeho Kim, Woosung Lee, Phil Ouk Nam, Junggeun Jee
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Publication number: 20220223616Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.Type: ApplicationFiled: April 1, 2022Publication date: July 14, 2022Inventors: Chang Sup LEE, Phil Ouk NAM, Sung Yun LEE, Chang Seok KANG
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Publication number: 20220139956Abstract: A semiconductor device may include a substrate, an electrode structure including electrodes stacked on the substrate, an upper semiconductor pattern penetrating at least a portion of the electrode structure, and a lower semiconductor pattern between the substrate and the upper semiconductor pattern. The upper semiconductor pattern includes a gap-filling portion and a sidewall portion extending from the gap-filling portion in a direction away from the substrate, the lower semiconductor pattern includes a concave top surface, the gap-filling portion fills a region enclosed by the concave top surface, a top surface of the gap-filling portion has a rounded shape that is deformed toward the substrate, and a thickness of the sidewall portion is less than a thickness of the gap-filling portion.Type: ApplicationFiled: January 19, 2022Publication date: May 5, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Ji-Hoon CHOI, Sunggil KIM, Seulye KIM, HongSuk KIM, Phil Ouk NAM, Jaeyoung AHN
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Patent number: 11296104Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.Type: GrantFiled: April 10, 2020Date of Patent: April 5, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang Sup Lee, Phil Ouk Nam, Sung Yun Lee, Chang Seok Kang
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Patent number: 11282856Abstract: A semiconductor device may include a substrate, an electrode structure including electrodes stacked on the substrate, an upper semiconductor pattern penetrating at least a portion of the electrode structure, and a lower semiconductor pattern between the substrate and the upper semiconductor pattern. The upper semiconductor pattern includes a gap-filling portion and a sidewall portion extending from the gap-filling portion in a direction away from the substrate, the lower semiconductor pattern includes a concave top surface, the gap-filling portion fills a region enclosed by the concave top surface, a top surface of the gap-filling portion has a rounded shape that is deformed toward the substrate, and a thickness of the sidewall portion is less than a thickness of the gap-filling portion.Type: GrantFiled: April 10, 2020Date of Patent: March 22, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Hoon Choi, Sunggil Kim, Seulye Kim, HongSuk Kim, Phil Ouk Nam, Jaeyoung Ahn
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Publication number: 20220068968Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.Type: ApplicationFiled: November 10, 2021Publication date: March 3, 2022Inventors: Ji Hoon CHOI, Sung Gil KIM, Seulye KIM, Jung Ho KIM, Hong Suk KIM, Phil Ouk NAM, Jae Young AHN, Han Jin LIM
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Patent number: 11189636Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.Type: GrantFiled: May 8, 2020Date of Patent: November 30, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Hoon Choi, Sung Gil Kim, Seulye Kim, Jung Ho Kim, Hong Suk Kim, Phil Ouk Nam, Jae Young Ahn, Han Jin Lim
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Publication number: 20210320123Abstract: Disclosed is a three-dimensional semiconductor memory device including a carbon-containing layer on a substrate, a plurality of electrode interlayer dielectric layers and a plurality of electrode layers that are alternately stacked on the carbon-containing layer, a cell vertical pattern that penetrates at least some of the electrode interlayer dielectric layers and the electrode layers, and a semiconductor pattern between the cell vertical pattern and the carbon-containing layer. The substrate includes a plurality of first grains. The semiconductor pattern includes a plurality of second grains. An average size of the second grains is less than an average size of the first grains.Type: ApplicationFiled: September 29, 2020Publication date: October 14, 2021Inventors: SANGSOO LEE, CHAEHO KIM, WOOSUNG LEE, PHIL OUK NAM, JUNGGEUN JEE
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Publication number: 20210108313Abstract: A semiconductor manufacturing apparatus including a process chamber and a boat having a support member supporting substrates arranged in a first direction. An inner tube encloses the boat and includes a slit along a side wall. A nozzle supplies a process gas and includes a gas injection port at a position corresponding to the slit. The gas injection port includes a first inlet and first outlet. The slit includes a second inlet and second outlet. A distance to an end of the first inlet from a center line that connects a center of the first inlet and a center of the second outlet is different from the distance from the center line to an end of the first outlet and/or a distance from the center line to an end of the second inlet is different from a distance from the center line to an end of the second outlet.Type: ApplicationFiled: August 3, 2020Publication date: April 15, 2021Inventors: Jae Hyun YANG, Sang Yub IE, Tae Yong KIM, Phil Ouk NAM
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Patent number: 10892278Abstract: A three-dimensional semiconductor device includes gate electrodes sequentially stacked on a substrate, a channel structure penetrating the gate electrodes and being connected to the substrate, an insulating gap-fill pattern provided within the channel structure and surrounded by the channel structure as viewed in a plan view, and a conductive pattern on the insulating gap-fill pattern. At least a portion of the insulating gap-fill pattern is received in the conductive pattern, and at least a portion of the conductive pattern is interposed between at least that portion of the insulating gap-fill pattern and the channel structure.Type: GrantFiled: July 11, 2019Date of Patent: January 12, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Hoon Choi, Sunggil Kim, Seulye Kim, Hongsuk Kim, Phil Ouk Nam, Jaeyoung Ahn
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Patent number: 10756185Abstract: A semiconductor device includes a substrate, a plurality of gate electrodes extending in a first direction parallel to an upper surface of a substrate on the substrate, and alternately arranged with an interlayer insulating layer in a second direction perpendicular to the upper surface of the substrate, a vertical channel layer on a sidewall of a vertical channel hole extending in the second direction by penetrating through the plurality of gate electrodes and the interlayer insulating layer, and connected to the upper surface of the substrate, and a first gap-fill insulating layer formed in the vertical channel hole and including an outer wall contacting the vertical channel layer and an inner wall opposite the outer wall, wherein a part of the inner wall forms a striation extending in the second direction.Type: GrantFiled: July 11, 2017Date of Patent: August 25, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-hoon Choi, Hong-suk Kim, Sung-gil Kim, Phil-ouk Nam, Seul-ye Kim, Han-jin Lim, Jae-young Ahn
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Publication number: 20200266213Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.Type: ApplicationFiled: May 8, 2020Publication date: August 20, 2020Inventors: Ji Hoon CHOI, Sung Gil KIM, Seulye KIM, Jung Ho KIM, Hong Suk KIM, Phil Ouk NAM, Jae Young AHN, Han Jin LIM
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Publication number: 20200243554Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.Type: ApplicationFiled: April 10, 2020Publication date: July 30, 2020Inventors: Chang Sup LEE, Phil Ouk NAM, Sung Yun LEE, Chang Seok KANG
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Publication number: 20200243558Abstract: A semiconductor device may include a substrate, an electrode structure including electrodes stacked on the substrate, an upper semiconductor pattern penetrating at least a portion of the electrode structure, and a lower semiconductor pattern between the substrate and the upper semiconductor pattern. The upper semiconductor pattern includes a gap-filling portion and a sidewall portion extending from the gap-filling portion in a direction away from the substrate, the lower semiconductor pattern includes a concave top surface, the gap-filling portion fills a region enclosed by the concave top surface, a top surface of the gap-filling portion has a rounded shape that is deformed toward the substrate, and a thickness of the sidewall portion is less than a thickness of the gap-filling portion.Type: ApplicationFiled: April 10, 2020Publication date: July 30, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Ji-Hoon CHOI, Sunggil KIM, Seulye KIM, HongSuk KIM, Phil Ouk NAM, Jaeyoung AHN
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Patent number: 10727115Abstract: Provided is a semiconductor device including a lower layer structure on a substrate, the lower layer structure having different thicknesses on first and second regions of the substrate, the lower layer structure including an electrode layer at a top and an insulating layer thereunder, an etch stop layer on the lower layer structure, an upper layer structure on the etch stop layer, the etch stop layer having an etch selectivity to the upper and lower layer structures, first and second contact plugs filling first and second openings defined in the upper layer structure and the etch stop layer on the first and second regions, respectively, and contacting corresponding electrode layers of the lower layer structure, respectively, such that one of the first and second contact plugs downwardly extends further with respect to a bottom of the etch stop layer than the other one of the first and second contact plugs.Type: GrantFiled: July 2, 2019Date of Patent: July 28, 2020Assignee: Samsung Electronics co., Ltd.Inventors: Phil Ouk Nam, Jaeyoung Ahn, Sangsoo Lee
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Patent number: 10685972Abstract: The inventive concepts provide semiconductor memory devices and methods for fabricating the same. The semiconductor memory device may include a plurality of gates vertically stacked on a substrate, a vertical channel filling a channel hole vertically penetrating the plurality of gates, and a memory layer vertically extending on an inner sidewall of the channel. The vertical channel may include a lower channel filling a lower region of the channel hole and electrically connected to the substrate, and an upper channel filling an upper region of the channel hole and contacting the lower channel. The upper channel may extend along the memory layer and the lower channel in the upper region of the channel hole and may have a uniform thickness.Type: GrantFiled: September 26, 2014Date of Patent: June 16, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Sunggil Kim, Phil Ouk Nam, Gukhyon Yon, Sunghae Lee, Woojin Jang, Dongchul Yoo, Hunhyeong Lim, Junggeun Jee, Kihyun Hwang