Patents by Inventor Phil-Ouk Nam
Phil-Ouk Nam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180261618Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.Type: ApplicationFiled: October 2, 2017Publication date: September 13, 2018Inventors: Chang Sup LEE, Phil Ouk NAM, Sung Yun LEE, Chang Seok KANG
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Patent number: 10002875Abstract: A semiconductor device may include gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating the gate electrodes and the interlayer insulating layers, a gate dielectric layer between the gate electrodes and the channel layer, a filling insulation that fills at least a portion of an interior of the channel layer, a charge fixing layer between the channel layer and the filling insulation and including a high-k material and/or a metal, and a conductive pad connected to the channel layer and on the filling insulation. The conductive pad may be physically separated from the charge fixing layer.Type: GrantFiled: March 22, 2017Date of Patent: June 19, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Phil Ouk Nam, Hyung Joon Kim, Sung Gil Kim, Ji Hoon Choi, Seulye Kim, Hong Suk Kim, Jae Young Ahn
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Patent number: 9997534Abstract: A vertical memory device includes a substrate, a channel on the substrate, extending in a vertical direction with respect to a top surface of the substrate, and including a protrusion at a lower portion of the channel, the protrusion extending in a parallel direction with respect to the top surface of the substrate, a semiconductor pattern connecting the protrusion and the substrate, and gate lines stacked and spaced apart from each other in the vertical direction, the gate lines on the protrusion and the semiconductor pattern and surrounding the channel.Type: GrantFiled: May 16, 2016Date of Patent: June 12, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Hoon Son, Kyung-Hyun Kim, Byeong-Ju Kim, Phil-Ouk Nam, Kwang Chul Park, Yeon-Sil Sohn, Jin-I Lee, Jong-Heun Lim, Won-Bong Jung, Kohji Kanamori
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Publication number: 20180122907Abstract: A semiconductor device includes a substrate, a plurality of gate electrodes extending in a first direction parallel to an upper surface of a substrate on the substrate, and alternately arranged with an interlayer insulating layer in a second direction perpendicular to the upper surface of the substrate, a vertical channel layer on a sidewall of a vertical channel hole extending in the second direction by penetrating through the plurality of gate electrodes and the interlayer insulating layer, and connected to the upper surface of the substrate, and a first gap-fill insulating layer formed in the vertical channel hole and including an outer wall contacting the vertical channel layer and an inner wall opposite the outer wall, wherein a part of the inner wall forms a striation extending in the second direction.Type: ApplicationFiled: July 11, 2017Publication date: May 3, 2018Inventors: Ji-hoon CHOI, Hong-suk KIM, Sung-gil KIM, Phil-ouk NAM, Seul-ye KIM, Han-jin LIM, Jae-young AHN
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Patent number: 9953999Abstract: In one embodiment, the semiconductor device includes a stack of alternating first interlayer insulating layers and gate electrode layers on a substrate. At least one of the gate electrode layers has a first portion and a second portion. The second portion forms an end portion of the at least one gate electrode layer, and a bottom surface of the second portion is at a lower level than a bottom surface of the first portion. A contact plug extends from the second portion.Type: GrantFiled: December 12, 2016Date of Patent: April 24, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Phil Ouk Nam, Sung Gil Kim, Seulye Kim, Hong Suk Kim, Jae Young Ahn, Ji Hoon Choi
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Publication number: 20180108672Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.Type: ApplicationFiled: April 11, 2017Publication date: April 19, 2018Inventors: Ji Hoon CHOI, Sung Gil KIM, Seulye KIM, Jung Ho KIM, Hong Suk KIM, Phil Ouk NAM, Jae Young AHN, Han Jin LIM
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Publication number: 20180097006Abstract: A semiconductor memory device may include: a stacking structure including a plurality of insulating layers and a plurality of gate electrodes alternately stacked on a substrate; a lower semiconductor pattern that protrudes from the top of the substrate; a vertical insulating pattern that extends in a vertical direction from the substrate and penetrates the stacking structure; and a vertical channel pattern on the inner surface of the vertical insulating pattern and contacting the lower semiconductor pattern, wherein an upper part of the lower semiconductor pattern includes a recess region including a curve-shaped profile, and in the recess region, the outer surface of a lower part of the vertical channel pattern contacts the lower semiconductor pattern along a curve of the recess region.Type: ApplicationFiled: April 6, 2017Publication date: April 5, 2018Inventors: Sung Gil Kim, Ji-Hoon Choi, Dongkyum Kim, Jintae Noh, Seulye Kim, Hong Suk Kim, Phil Ouk Nam, Jaeyoung Ahn
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Patent number: 9905568Abstract: A nonvolatile memory device includes a conductive line disposed on a substrate and vertically extended from the substrate, a first channel layer disposed on the substrate and vertically extended from the substrate, wherein the first channel layer is spaced apart from the conductive line, a second channel layer vertically extended from the substrate, wherein the second channel layer is disposed between the first channel layer and the conductive line, a first gate electrode disposed between the conductive line and the second channel layer, wherein the first gate electrode includes a first portion having a first thickness and a second portion having a second thickness that is different from the first thickness, and a second gate electrode disposed between the first channel layer and the second channel layer, wherein the second gate electrode has the second thickness.Type: GrantFiled: August 30, 2016Date of Patent: February 27, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-Hoon Son, Jong-Won Kim, Chang-Seok Kang, Young-Woo Park, Jae-Duk Lee, Kyung-Hyun Kim, Byeong-Ju Kim, Phil-Ouk Nam, Kwang-Chul Park, Yeon-Sil Sohn, Jin-I Lee, Won-Bong Jung
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Publication number: 20180053775Abstract: A semiconductor device may include gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating the gate electrodes and the interlayer insulating layers, a gate dielectric layer between the gate electrodes and the channel layer, a filling insulation that fills at least a portion of an interior of the channel layer, a charge fixing layer between the channel layer and the filling insulation and including a high-k material and/or a metal, and a conductive pad connected to the channel layer and on the filling insulation. The conductive pad may be physically separated from the charge fixing layer.Type: ApplicationFiled: March 22, 2017Publication date: February 22, 2018Inventors: Phil Ouk Nam, Hyung Joon Kim, Sung Gil Kim, Ji Hoon Choi, Seulye Kim, Hong Suk Kim, Jae Young Ahn
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Patent number: 9899411Abstract: A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.Type: GrantFiled: January 24, 2017Date of Patent: February 20, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dongchul Yoo, Phil Ouk Nam, Junkyu Yang, Woong Lee, Woosung Lee, JinGyun Kim, Daehong Eom
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Patent number: 9893077Abstract: A memory device, including a first memory region including a first substrate, a plurality of first semiconductor devices on the first substrate, and a first interlayer insulating layer covering the plurality of first semiconductor devices; and a second memory region including a second substrate on the first interlayer insulating layer and a plurality of second semiconductor devices on the second substrate, the second substrate including a first region in a plurality of grooves in the first interlayer insulating layer and a second region including grains extending from the first region, the second region being on an upper surface of the first interlayer insulating layer.Type: GrantFiled: February 22, 2016Date of Patent: February 13, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Phil Ouk Nam, Yong Hoon Son, Kyung Hyun Kim, Byeong Ju Kim, Kwang Chul Park, Yeon Sil Sohn, Jin I Lee, Jong Heun Lim, Won Bong Jung
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Publication number: 20180040628Abstract: A vertical-type memory device may include a channel layer vertically extending on a substrate, a ground selection transistor at a side of the channel layer on the substrate, the ground selection transistor including a first gate insulation portion and a first replacement gate electrode, an etch control layer on the first replacement gate electrode, and a memory cell on the etch control layer, the memory cell including a second gate insulation portion and a second replacement gate electrode. The etch control layer may include a polysilicon layer doped with carbon, N-type impurities, or P-type impurities, or may include a polysilicon oxide layer comprising carbon, N-type impurities, or P-type impurities. A thickness of the first replacement gate electrode may be the same as a thickness of the second replacement gate electrode, or the first replacement gate electrode may be thicker than the second.Type: ApplicationFiled: March 20, 2017Publication date: February 8, 2018Inventors: Phil-ouk Nam, Sung-gil KIM, Ji-hoon CHOI, SeuI-ye KIM, Jae-young AHN, Hong-suk KIM
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Publication number: 20180026046Abstract: In one embodiment, the semiconductor device includes a stack of alternating first interlayer insulating layers and gate electrode layers on a substrate. At least one of the gate electrode layers has a first portion and a second portion. The second portion forms an end portion of the at least one gate electrode layer, and a bottom surface of the second portion is at a lower level than a bottom surface of the first portion. A contact plug extends from the second portion.Type: ApplicationFiled: December 12, 2016Publication date: January 25, 2018Inventors: Phil Ouk NAM, Sung Gil KIM, Seulye KIM, Hong Suk KIM, Jae Young AHN, Ji Hoon CHOI
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Patent number: 9871055Abstract: A vertical-type memory device may include a channel layer vertically extending on a substrate, a ground selection transistor at a side of the channel layer on the substrate, the ground selection transistor including a first gate insulation portion and a first replacement gate electrode, an etch control layer on the first replacement gate electrode, and a memory cell on the etch control layer, the memory cell including a second gate insulation portion and a second replacement gate electrode. The etch control layer may include a polysilicon layer doped with carbon, N-type impurities, or P-type impurities, or may include a polysilicon oxide layer comprising carbon, N-type impurities, or P-type impurities. A thickness of the first replacement gate electrode may be the same as a thickness of the second replacement gate electrode, or the first replacement gate electrode may be thicker than the second.Type: GrantFiled: March 20, 2017Date of Patent: January 16, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Phil-ouk Nam, Sung-gil Kim, Ji-hoon Choi, Seul-ye Kim, Jae-young Ahn, Hong-suk Kim
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Publication number: 20170287929Abstract: The inventive concepts provide semiconductor memory devices and methods for fabricating the same. The semiconductor memory device may include a plurality of gates vertically stacked on a substrate, a vertical channel filling a channel hole vertically penetrating the plurality of gates, and a memory layer vertically extending on an inner sidewall of the channel. The vertical channel may include a lower channel filling a lower region of the channel hole and electrically connected to the substrate, and an upper channel filling an upper region of the channel hole and contacting the lower channel. The upper channel may extend along the memory layer and the lower channel in the upper region of the channel hole and may have a uniform thickness.Type: ApplicationFiled: September 26, 2014Publication date: October 5, 2017Inventors: Sunggil KIM, Phil Ouk NAM, Gukhyon YON, Sunghae LEE, Woojin JANG, Dongchul YOO, Hunhyeong LIM, Junggeun JEE, Kihyun HWANG
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Patent number: 9716181Abstract: A semiconductor device includes a polycrystalline semiconductor layer on a substrate, first and second stacks on the polycrystalline semiconductor layer, the first and second stacks extending in a first direction, a separation trench between the first and second stacks and extending in the first direction, the separation trench separating the first and second stacks in a second direction crossing the first direction, and vertical channel structures vertically passing through each of the first and second stacks, wherein the polycrystalline semiconductor layer includes a first grain region and a second grain region in contact with each other, the first and second grain region being adjacent to each other along the second direction, and wherein each of the first and second grain regions includes a plurality of crystal grains, each crystal grain having a longitudinal axis parallel to the second direction.Type: GrantFiled: June 8, 2016Date of Patent: July 25, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Phil Ouk Nam, Yong-Hoon Son, Kyunghyun Kim, Byeongju Kim, Kwangchul Park, Yeon-Sil Sohn, Jin-l Lee, JongHeun Lim, Wonbong Jung
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Publication number: 20170133400Abstract: A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.Type: ApplicationFiled: January 24, 2017Publication date: May 11, 2017Inventors: Dongchul YOO, Phil Ouk NAM, Junkyu YANG, Woong LEE, Woosung LEE, JinGyun KIM, Daehong EOM
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Publication number: 20170098656Abstract: A semiconductor memory device includes insulating patterns and gate patterns alternately stacked on a substrate, a channel structure that intersects the insulating patterns and the gate patterns and connected to the substrate, a charge storage structure between the channel structure and the gate patterns, and a contact structure on the substrate at a side of the insulating patterns and the gate patterns. One of the gate patterns includes a first barrier pattern between a first insulating pattern of the insulating patterns and a second insulating pattern of the insulating patterns adjacent the first insulating pattern in a first direction perpendicular to a main surface of the substrate, the first barrier pattern defining a concave region between a first portion of the first barrier pattern extending along the first insulating pattern and a second portion extending along the second insulating pattern, and a metal pattern in the concave region.Type: ApplicationFiled: August 25, 2016Publication date: April 6, 2017Inventors: Yong-Hoon Son, Kyunghyun KIM, Byeongju KIM, Phil Ouk NAM, Kwangchul PARK, Yeon-Sil SOHN, Jin-I LEE, Wonbong Jung
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Publication number: 20170084532Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a vertical direction with respect to a top surface of the substrate, a plurality of non-metal gate patterns surrounding the channels and being stacked on top of each other and spaced apart from each other along the vertical direction, and a plurality of metal gate patterns stacked on top of each other. The metal gate patterns are spaced apart from each other along the vertical direction. Each of the metal gate patterns surrounds a corresponding one of the non-metal gate patterns.Type: ApplicationFiled: September 21, 2016Publication date: March 23, 2017Inventors: Yong-Hoon SON, Cha-Dong YEO, Han-Mei CHOI, Kyung-Hyun KIM, Phil-Ouk NAM, Kwang-Chui PARK, Yeon-Sil SOHN, Jin-I LEE, Won-Bong JUNG
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Publication number: 20170069637Abstract: A nonvolatile memory device includes a conductive line disposed on a substrate and vertically extended from the substrate, a first channel layer disposed on the substrate and vertically extended from the substrate, wherein the first channel layer is spaced apart from the conductive line, a second channel layer vertically extended from the substrate, wherein the second channel layer is disposed between the first channel layer and the conductive line, a first gate electrode disposed between the conductive line and the second channel layer, wherein the first gate electrode includes a first portion having a first thickness and a second portion having a second thickness that is different from the first thickness, and a second gate electrode disposed between the first channel layer and the second channel layer, wherein the second gate electrode has the second thickness.Type: ApplicationFiled: August 30, 2016Publication date: March 9, 2017Inventors: YONG-HOON SON, JONG-WON KIM, CHANG-SEOK KANG, YOUNG-WOO PARK, JAE-DUK LEE, KYUNG-HYUN KIM, BYEONG-JU KIM, PHIL-OUK NAM, KWANG-CHUL PARK, YEON-SIL SOHN, JIN-I LEE, WON-BONG JUNG