Patents by Inventor Phil-Ouk Nam
Phil-Ouk Nam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170062471Abstract: A semiconductor memory device is disclosed. The device may include a stack including gate electrodes stacked on a substrate in a vertical direction and insulating patterns interposed between the gate electrodes, vertical channels passing through the stack and connected to the substrate, a tunnel insulating layer enclosing each of the vertical channels, charge storing patterns provided between the tunnel insulating layer and the gate electrodes and spaced apart from each other in the vertical direction, blocking insulating patterns provided between the charge storing patterns and the gate electrodes and spaced apart from each other in the vertical direction, and a bit line crossing the stack and connected to the vertical channels. The blocking insulating patterns may have a vertical thickness that is greater than that of the gate electrodes.Type: ApplicationFiled: August 27, 2016Publication date: March 2, 2017Inventors: Yong-Hoon SON, JIN-I LEE, Kyunghyun KIM, Byeongju KIM, Phil Ouk NAM, Kwangchul PARK, Yeon-Sil SOHN, JongHeun LIM, Wonbong Jung
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Patent number: 9559111Abstract: A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.Type: GrantFiled: July 2, 2015Date of Patent: January 31, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dongchul Yoo, Phil Ouk Nam, Junkyu Yang, Woong Lee, Woosung Lee, JinGyun Kim, Daehong Eom
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Publication number: 20170025545Abstract: A semiconductor device includes a polycrystalline semiconductor layer on a substrate, first and second stacks on the polycrystalline semiconductor layer, the first and second stacks extending in a first direction, a separation trench between the first and second stacks and extending in the first direction, the separation trench separating the first and second stacks in a second direction crossing the first direction, and vertical channel structures vertically passing through each of the first and second stacks, wherein the polycrystalline semiconductor layer includes a first grain region and a second grain region in contact with each other, the first and second grain region being adjacent to each other along the second direction, and wherein each of the first and second grain regions includes a plurality of crystal grains, each crystal grain having a longitudinal axis parallel to the second direction.Type: ApplicationFiled: June 8, 2016Publication date: January 26, 2017Inventors: Phil Ouk NAM, Yong-Hoon SON, Kyunghyun KIM, Byeongju KIM, Kwangchul PARK, Yeon-Sil SOHN, Jin-I LEE, JongHeun LIM, Wonbong JUNG
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Publication number: 20160358927Abstract: A memory device, including a first memory region including a first substrate, a plurality of first semiconductor devices on the first substrate, and a first interlayer insulating layer covering the plurality of first semiconductor devices; and a second memory region including a second substrate on the first interlayer insulating layer and a plurality of second semiconductor devices on the second substrate, the second substrate including a first region in a plurality of grooves in the first interlayer insulating layer and a second region including grains extending from the first region, the second region being on an upper surface of the first interlayer insulating layer.Type: ApplicationFiled: February 22, 2016Publication date: December 8, 2016Inventors: Phil Ouk NAM, Yong Hoon SON, Kyung Hyun KIM, Byeong Ju KIM, Kwang Chul PARK, Yeon Sil SOHN, Jin I LEE, Jong Heun LIM, Won Bong JUNG
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Publication number: 20160343730Abstract: A vertical memory device includes a substrate, a channel on the substrate, extending in a vertical direction with respect to a top surface of the substrate, and including a protrusion at a lower portion of the channel, the protrusion extending in a parallel direction with respect to the top surface of the substrate, a semiconductor pattern connecting the protrusion and the substrate, and gate lines stacked and spaced apart from each other in the vertical direction, the gate lines on the protrusion and the semiconductor pattern and surrounding the channel.Type: ApplicationFiled: May 16, 2016Publication date: November 24, 2016Inventors: Yong-Hoon Son, Kyung-Hyun KIM, Byeong-Ju KIM, Phil-Ouk NAM, Kwang Chul PARK, Yeon-Sil SOHN, Jin-I LEE, Jong-Heun LIM, Won-Bong JUNG, Kohji KANAMORI
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Patent number: 9461061Abstract: A method of manufacturing a vertical memory device includes forming alternating and repeating insulating interlayers and sacrificial layers on a substrate, the sacrificial layers including polysilicon or amorphous silicon, forming channel holes through the insulating interlayers and the sacrificial layers, forming channels in the channel holes, etching portions of the insulating interlayers and the sacrificial layers between adjacent channels to form openings, removing the sacrificial layers to form gaps between the insulating interlayers, and forming gate lines in the gaps.Type: GrantFiled: November 18, 2014Date of Patent: October 4, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Phil-Ouk Nam, Jun-Kyu Yang, Jin-Gyun Kim, Jae-Young Ahn, Hun Hyeong Lim, Ki-Hyun Hwang
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Patent number: 9431414Abstract: Nonvolatile memory devices include at least four cylindrical-shaped channel regions, which extend vertically from portions of a substrate located at respective vertices of at least one rhomboid when viewed in a vertical direction relative to a surface of the substrate. A charge storage layer (e.g., ONO layer) is provided on an outer sidewall of each of the cylindrical-shaped channel regions. In addition, to achieve a high degree of integration, a plurality of vertically-stacked gate electrodes are provided, which extend adjacent each of the cylindrical-shaped channel regions.Type: GrantFiled: October 17, 2014Date of Patent: August 30, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Byong-Hyun Jang, Dong-Chul Yoo, Ki-Hyun Hwang, Phil-Ouk Nam, Jae-Young Ahn
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Patent number: 9431416Abstract: A vertical-type nonvolatile memory device includes a first vertical channel structure, and first and second stacked structure. The first vertical channel structure extends vertically on a substrate. The first stacked structure includes gate electrodes and first interlayer insulating layers. The gate layers and the first interlayer insulating layers are alternately and vertically stacked on each other. The first stacked structure is disposed on a first sidewall of the first vertical channel structure. The second stacked structure includes first sacrificial layers and second interlayer insulating layers. The first sacrificial layers and the second interlayer insulating layers are alternately and vertically stacked on each other. The second stacked structure is disposed on a second sidewall of the first vertical channel structure. The first sacrificial layers is formed of a polysilicon layer.Type: GrantFiled: October 28, 2014Date of Patent: August 30, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Phil-ouk Nam, Jun-kyu Yang, Hun-hyeong Lim, Ki-hyun Hwang, Jae-young Ahn, Dong-chul Yoo
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Patent number: 9324730Abstract: A vertical memory device including a substrate including first regions and a second region; a plurality of channels in the first regions, the plurality of channels extending in a first direction substantially perpendicular to a top surface of the substrate; a charge storage structure on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate; a plurality of gate electrodes in the first regions, the plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in the first direction; and a plurality of supporters in the second region, the plurality of supporters spaced apart from each other in a third direction substantially perpendicular to the first direction and the second direction, the plurality of supporters contacting a sidewall of at least one gate electrode.Type: GrantFiled: January 21, 2015Date of Patent: April 26, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Phil-Ouk Nam, Dong-Chul Yoo, Bi-O Kim, Jae-Young Ahn, Byong-Hyun Jang, Ki-Hyun Hwang
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Publication number: 20150357346Abstract: A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.Type: ApplicationFiled: August 20, 2015Publication date: December 10, 2015Inventors: BYONG-HYUN JANG, JUHYUNG KIM, WOON KYUNG LEE, JAEGOO LEE, CHAEHO KIM, JUNKYU YANG, PHIL OUK NAM, JAEYOUNG AHN, KlHYUN HWANG
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Publication number: 20150311214Abstract: A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.Type: ApplicationFiled: July 2, 2015Publication date: October 29, 2015Inventors: Dongchul YOO, Phil Ouk NAM, Junkyu YANG, Woong LEE, Woosung LEE, JinGyun KIM, Daehong EOM
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Patent number: 9130054Abstract: A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.Type: GrantFiled: March 13, 2013Date of Patent: September 8, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byong-hyun Jang, Juhyung Kim, Woonkyung Lee, Jaegoo Lee, Chaeho Kim, Junkyu Yang, Phil Ouk Nam, Jaeyoung Ahn, Kihyun Hwang
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Publication number: 20150206900Abstract: A vertical memory device including a substrate including first regions and a second region; a plurality of channels in the first regions, the plurality of channels extending in a first direction substantially perpendicular to a top surface of the substrate; a charge storage structure on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate; a plurality of gate electrodes in the first regions, the plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in the first direction; and a plurality of supporters in the second region, the plurality of supporters spaced apart from each other in a third direction substantially perpendicular to the first direction and the second direction, the plurality of supporters contacting a sidewall of at least one gate electrode.Type: ApplicationFiled: January 21, 2015Publication date: July 23, 2015Inventors: Phil-Ouk NAM, Dong-Chul YOO, Bi-O KIM, Jae-Young AHN, Byong-Hyun JANG, Ki-Hyun HWANG
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Patent number: 9082659Abstract: A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.Type: GrantFiled: March 10, 2015Date of Patent: July 14, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Phil-Ouk Nam, Jun-Kyu Yang, Byong-Hyun Jang, Ki-Hyun Hwang, Jae-Young Ahn
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Patent number: 9076879Abstract: A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.Type: GrantFiled: August 23, 2013Date of Patent: July 7, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dongchul Yoo, Phil Ouk Nam, Junkyu Yang, Woong Lee, Woosung Lee, JinGyun Kim, Daehong Eom
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Publication number: 20150187790Abstract: A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.Type: ApplicationFiled: March 10, 2015Publication date: July 2, 2015Inventors: Phil-Ouk Nam, Jun-Kyu Yang, Byong-Hyun Jang, Ki-Hyun Hwang, Jae-Young Ahn
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Publication number: 20150145021Abstract: Nonvolatile memory devices include at least four cylindrical-shaped channel regions, which extend vertically from portions of a substrate located at respective vertices of at least one rhomboid when viewed in a vertical direction relative to a surface of the substrate. A charge storage layer (e.g., ONO layer) is provided on an outer sidewall of each of the cylindrical-shaped channel regions. In addition, to achieve a high degree of integration, a plurality of vertically-stacked gate electrodes are provided, which extend adjacent each of the cylindrical-shaped channel regions.Type: ApplicationFiled: October 17, 2014Publication date: May 28, 2015Inventors: Byong-Hyun Jang, Dong-Chul Yoo, Ki-Hyun Hwang, Phil-Ouk Nam, Jae-Young Ahn
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Publication number: 20150137210Abstract: A method of manufacturing a vertical memory device includes forming alternating and repeating insulating interlayers and sacrificial layers on a substrate, the sacrificial layers including polysilicon or amorphous silicon, forming channel holes through the insulating interlayers and the sacrificial layers, forming channels in the channel holes, etching portions of the insulating interlayers and the sacrificial layers between adjacent channels to form openings, removing the sacrificial layers to form gaps between the insulating interlayers, and forming gate lines in the gaps.Type: ApplicationFiled: November 18, 2014Publication date: May 21, 2015Inventors: Phil-Ouk NAM, Jun-Kyu YANG, Jin-Gyun KIM, Jae-Young AHN, Hun Hyeong LIM, Ki-Hyun HWANG
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Publication number: 20150115348Abstract: A vertical-type nonvolatile memory device includes a first vertical channel structure, and first and second stacked structure. The first vertical channel structure extends vertically on a substrate. The first stacked structure includes gate electrodes and first interlayer insulating layers. The gate layers and the first interlayer insulating layers are alternately and vertically stacked on each other. The first stacked structure is disposed on a first sidewall of the first vertical channel structure. The second stacked structure includes first sacrificial layers and second interlayer insulating layers. The first sacrificial layers and the second interlayer insulating layers are alternately and vertically stacked on each other. The second stacked structure is disposed on a second sidewall of the first vertical channel structure. The first sacrificial layers is formed of a polysilicon layer.Type: ApplicationFiled: October 28, 2014Publication date: April 30, 2015Inventors: Phil-ouk Nam, Jun-kyu Yang, Hun-hyeong Lim, Ki-hyun Hwang, Jae-young Ahn, Dong-chul Yoo
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Patent number: 8987805Abstract: A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.Type: GrantFiled: August 20, 2013Date of Patent: March 24, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Phil-Ouk Nam, Jun-Kyu Yang, Byong-Hyun Jang, Ki-Hyun Hwang, Jae-Young Ahn