Abstract: A method of manufacturing a semiconductor layer is provided. In a first deposition during a first period of time, at least one Group IIIA element and at least one Group VIA element are deposited on a substrate or on a layer optional disposed on the substrate such as a back-electrode. During a second deposition during a second period of time, at least one Group IB element and the at least one group VIA element are deposited on the substrate or the optional layer. The one Group IB element combines with the Group VIA element to form a IB2VIA composition. A first deposition state is monitored, during the second deposition by making a first plurality of measurements of a first deposition state. The second deposition is terminated or attenuated based on a function of the first plurality of measurements of the indicia of the first deposition state.

Abstract: A method of manufacturing a semiconductor layer is provided. In a first deposition during a first period of time, at least one Group IIIA element and at least one Group VIA element are deposited on a substrate or on a layer optional disposed on the substrate such as a back-electrode. During a second deposition during a second period of time, at least one Group IB element and the at least one group VIA element are deposited on the substrate or the optional layer. The one Group IB element combines with the Group VIA element to form a IB2VIA composition. A first deposition state is monitored, during the second deposition by making a first plurality of measurements of a first deposition state. The second deposition is terminated or attenuated based on a function of the first plurality of measurements of the indicia of the first deposition state.

Abstract: A method of manufacturing a semiconductor layer is provided. In a first deposition during a first period of time, at least one Group IIIA element and at least one Group VIA element are deposited on a substrate or on a layer optional disposed on the substrate such as a back-electrode. During a second deposition during a second period of time, at least one Group IB element and the at least one group VIA element are deposited on the substrate or the optional layer. The one Group IB element combines with the Group VIA element to form a IB2VIA composition. A first deposition state is monitored, during the second deposition by making a first plurality of measurements of a first deposition state. The second deposition is terminated or attenuated based on a function of the first plurality of measurements of the indicia of the first deposition state.

Abstract: A method and apparatus for forming a nitrided gate dielectric layer. The method includes generating a nitrogen-containing plasma in a processing chamber via a smooth-varying modulated RF power source to reduce electron temperature spike. Field effect transistor channel mobility and gate leakage current results are improved when the power source is smooth-varying modulated, as compared to square-wave modulated.

Abstract: A method of manufacturing a semiconductor layer is provided. In a first deposition during a first period of time, at least one Group IIIA element and at least one Group VIA element are deposited on a substrate or on a layer optional disposed on the substrate such as a back-electrode. During a second deposition during a second period of time, at least one Group IB element and the at least one group VIA element are deposited on the substrate or the optional layer. The one Group IB element combines with the Group VIA element to form a IB2VIA composition. A first deposition state is monitored, during the second deposition by making a first plurality of measurements of a first deposition state. The second deposition is terminated or attenuated based on a function of the first plurality of measurements of the indicia of the first deposition state.

Abstract: A method for fabricating a gate dielectric of a field effect transistor is disclosed herein. In one embodiment, the method includes the steps of removing a native oxide layer, forming an oxide layer, forming a gate dielectric layer over the oxide layer, forming an oxide layer over the gate dielectric layer, and annealing the layers and underlying thermal oxide/silicon interface. Optionally, the oxide layer may be nitridized prior to forming the gate dielectric layer. In one embodiment, at least portions of the method are performed using at least one processing reactor arranged on a cluster tool. In one embodiment, the oxide layer on the substrate is formed by depositing the oxide layer and the oxide layer on the gate dielectric layer is formed by oxidizing at least a portion of the gate dielectric layer using an oxygen-containing plasma.

Abstract: A method for fabricating a gate dielectric of a field effect transistor is disclosed herein. In one embodiment, the method includes the steps of removing a native oxide layer, forming an oxide layer, forming a gate dielectric layer over the oxide layer, oxidizing the gate dielectric layer, and annealing the layers and underlying thermal oxide/silicon interface. Optionally, the oxide layer may be nitridized prior to forming the gate dielectric layer. Optionally, the gate dielectric layer may be nitridized prior to oxidizing the gate dielectric layer. In one embodiment, at least portions of the method are performed using processing reactors arranged on a cluster tool.

Abstract: A method and apparatus for forming a nitrided gate dielectric layer. The method includes generating a nitrogen-containing plasma in a processing chamber via a smooth-varying modulated RF power source to reduce electron temperature spike. Field effect transistor channel mobility and gate leakage current results are improved when the power source is smooth-varying modulated, as compared to square-wave modulated.

Abstract: A method of forming a silicon oxynitride gate dielectric. The method includes providing a structure comprising a silicon film formed on a substrate. The structure is exposed to a first plasma comprising a nitrogen source to incorporate nitrogen into the silicon film. The structure is oxidized in an atmosphere comprising nitric oxide to form a silicon oxynitride gate dielectric on the structure. The structure is then exposed to a second plasma comprising a nitrogen source.

Abstract: A method and apparatus for forming a nitrided gate dielectric layer. The method includes generating a nitrogen-containing plasma in a processing chamber via a smooth-varying modulated RF power source to reduce electron temperature spike. Field effect transistor channel mobility and gate leakage current results are improved when the power source is smooth-varying modulated, as compared to square-wave modulated.

Abstract: Methods for forming dielectric materials on a substrate in a single cluster tool are provided. In one embodiment, the method includes providing a cluster tool having a plurality of deposition chambers, depositing a metal-containing oxide layer on a substrate in a first chamber of the cluster tool, treating the metal-containing oxide layer with an insert plasma process in a second chamber of the cluster tool, annealing the metal-containing oxide layer in a third chamber of the cluster tool, and depositing a gate electrode layer on the annealed substrate in a fourth chamber of the cluster tool.

Abstract: In one embodiment, a method for forming a dielectric stack on a substrate is provided which includes depositing a first layer of a dielectric material on a substrate surface, exposing the first layer to a nitridation process, depositing a second layer of the dielectric material on the first layer, exposing the second layer to the nitridation process, and exposing the substrate to an anneal process. In another embodiment, a method for forming a dielectric material on a substrate is provided which includes depositing a metal oxide layer substantially free of silicon on a substrate surface, exposing the metal oxide layer to a nitridation process, and exposing the substrate to an anneal process.

Abstract: A method and apparatus for forming a nitrided gate dielectric layer. The method includes generating a nitrogen-containing plasma in a processing chamber via a smooth-varying modulated RF power source to reduce electron temperature spike. Field effect transistor channel mobility and gate leakage current results are improved when the power source is smooth-varying modulated, as compared to square-wave modulated.