Patents by Inventor Philip A. Kraus

Philip A. Kraus has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130045587
    Abstract: Epitaxial films are grown by alternately exposed to precursor dosing regions, inert gas plasma regions, hydrogen-containing plasma regions, chlorine-containing plasma and metrology regions, or regions where an atomic hydrogen source is located. Alternately, laser irradiation techniques may be substituted for the plasma energy in some of the processing regions. The film growth process can be implemented at substrate temperatures between about 25 C and about 600 C, together with optional exposures to laser irradiation to cause the surface of the film to melt or to experience a near-melt condition.
    Type: Application
    Filed: August 18, 2011
    Publication date: February 21, 2013
    Applicant: Intermolecular, Inc.
    Inventors: Philip A. Kraus, Dipankar Pramanik, Boris Borisov
  • Patent number: 8377803
    Abstract: A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: February 19, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Philip A. Kraus, Thai Cheng Chua, Sandeep Nijhawan
  • Patent number: 8323754
    Abstract: In one embodiment, a method for forming a dielectric stack on a substrate is provided which includes depositing a first layer of a dielectric material on a substrate surface, exposing the first layer to a nitridation process, depositing a second layer of the dielectric material on the first layer, exposing the second layer to the nitridation process, and exposing the substrate to an anneal process. In another embodiment, a method for forming a dielectric material on a substrate is provided which includes depositing a metal oxide layer substantially free of silicon on a substrate surface, exposing the metal oxide layer to a nitridation process, and exposing the substrate to an anneal process.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: December 4, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Christopher Olsen, Pravin K. Narwankar, Shreyas S. Kher, Randhir Thakur, Shankar Muthukrishnan, Philip A. Kraus
  • Patent number: 8318590
    Abstract: A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: November 27, 2012
    Assignee: Intermolecular, Inc.
    Inventors: Philip A. Kraus, Thai Cheng Chua, Sandeep Nijhawan
  • Publication number: 20120208357
    Abstract: A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films.
    Type: Application
    Filed: February 17, 2012
    Publication date: August 16, 2012
    Applicant: Intermolecular, Inc.
    Inventors: Philip A. Kraus, Sandeep Nijhawan, Thai Cheng Chua
  • Publication number: 20120208352
    Abstract: A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films.
    Type: Application
    Filed: February 16, 2012
    Publication date: August 16, 2012
    Applicant: Intermolecular, Inc.
    Inventors: Philip A. Kraus, Sandeep Nijhawan, Thai Cheng Chua
  • Patent number: 8143147
    Abstract: A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: March 27, 2012
    Assignee: Intermolecular, Inc.
    Inventors: Philip A. Kraus, Sandeep Nijhawan, Thai Cheng Chua
  • Patent number: 8110828
    Abstract: A method of manufacturing a semiconductor layer is provided. In a first deposition during a first period of time, at least one Group IIIA element and at least one Group VIA element are deposited on a substrate or on a layer optional disposed on the substrate such as a back-electrode. During a second deposition during a second period of time, at least one Group IB element and the at least one group VIA element are deposited on the substrate or the optional layer. The one Group IB element combines with the Group VIA element to form a IB2VIA composition. A first deposition state is monitored, during the second deposition by making a first plurality of measurements of a first deposition state. The second deposition is terminated or attenuated based on a function of the first plurality of measurements of the indicia of the first deposition state.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: February 7, 2012
    Assignee: Solyndra LLC
    Inventors: Vedapuram S. Achutharaman, Wen Chang, Tarpan Dixit, Philip Kraus
  • Publication number: 20110259391
    Abstract: A method of manufacturing a semiconductor layer is provided. In a first deposition during a first period of time, at least one Group IIIA element and at least one Group VIA element are deposited on a substrate or on a layer optional disposed on the substrate such as a back-electrode. During a second deposition during a second period of time, at least one Group IB element and the at least one group VIA element are deposited on the substrate or the optional layer. The one Group IB element combines with the Group VIA element to form a IB2VIA composition. A first deposition state is monitored, during the second deposition by making a first plurality of measurements of a first deposition state. The second deposition is terminated or attenuated based on a function of the first plurality of measurements of the indicia of the first deposition state.
    Type: Application
    Filed: June 9, 2011
    Publication date: October 27, 2011
    Inventors: Vedapuram S. Achutharaman, Wen Chang, Tarpan Dixit, Philip Kraus
  • Patent number: 7964418
    Abstract: A method of manufacturing a semiconductor layer is provided. In a first deposition during a first period of time, at least one Group IIIA element and at least one Group VIA element are deposited on a substrate or on a layer optional disposed on the substrate such as a back-electrode. During a second deposition during a second period of time, at least one Group IB element and the at least one group VIA element are deposited on the substrate or the optional layer. The one Group IB element combines with the Group VIA element to form a IB2VIA composition. A first deposition state is monitored, during the second deposition by making a first plurality of measurements of a first deposition state. The second deposition is terminated or attenuated based on a function of the first plurality of measurements of the indicia of the first deposition state.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: June 21, 2011
    Assignee: Solyndra LLC
    Inventors: Vedapuram S. Achutharaman, Wen Chang, Tarpan Dixit, Philip Kraus
  • Patent number: 7514373
    Abstract: A method and apparatus for forming a nitrided gate dielectric layer. The method includes generating a nitrogen-containing plasma in a processing chamber via a smooth-varying modulated RF power source to reduce electron temperature spike. Field effect transistor channel mobility and gate leakage current results are improved when the power source is smooth-varying modulated, as compared to square-wave modulated.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: April 7, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Philip A. Kraus, Thai Cheng Chua
  • Publication number: 20080041439
    Abstract: A method of manufacturing a semiconductor layer is provided. In a first deposition during a first period of time, at least one Group IIIA element and at least one Group VIA element are deposited on a substrate or on a layer optional disposed on the substrate such as a back-electrode. During a second deposition during a second period of time, at least one Group IB element and the at least one group VIA element are deposited on the substrate or the optional layer. The one Group IB element combines with the Group VIA element to form a IB2VIA composition. A first deposition state is monitored, during the second deposition by making a first plurality of measurements of a first deposition state. The second deposition is terminated or attenuated based on a function of the first plurality of measurements of the indicia of the first deposition state.
    Type: Application
    Filed: August 16, 2007
    Publication date: February 21, 2008
    Inventors: Vedapuram S. Achutharaman, Wen Chang, Tarpan Dixit, Philip Kraus
  • Publication number: 20070093013
    Abstract: A method for fabricating a gate dielectric of a field effect transistor is disclosed herein. In one embodiment, the method includes the steps of removing a native oxide layer, forming an oxide layer, forming a gate dielectric layer over the oxide layer, forming an oxide layer over the gate dielectric layer, and annealing the layers and underlying thermal oxide/silicon interface. Optionally, the oxide layer may be nitridized prior to forming the gate dielectric layer. In one embodiment, at least portions of the method are performed using at least one processing reactor arranged on a cluster tool. In one embodiment, the oxide layer on the substrate is formed by depositing the oxide layer and the oxide layer on the gate dielectric layer is formed by oxidizing at least a portion of the gate dielectric layer using an oxygen-containing plasma.
    Type: Application
    Filed: May 5, 2006
    Publication date: April 26, 2007
    Inventors: Thai Chua, Cory Czarnik, Andreas Hegedus, Christopher Olsen, Khaled Ahmed, Philip Kraus
  • Publication number: 20070093012
    Abstract: A method for fabricating a gate dielectric of a field effect transistor is disclosed herein. In one embodiment, the method includes the steps of removing a native oxide layer, forming an oxide layer, forming a gate dielectric layer over the oxide layer, oxidizing the gate dielectric layer, and annealing the layers and underlying thermal oxide/silicon interface. Optionally, the oxide layer may be nitridized prior to forming the gate dielectric layer. Optionally, the gate dielectric layer may be nitridized prior to oxidizing the gate dielectric layer. In one embodiment, at least portions of the method are performed using processing reactors arranged on a cluster tool.
    Type: Application
    Filed: October 20, 2005
    Publication date: April 26, 2007
    Inventors: Thai Chua, Cory Czarnik, Christopher Olsen, Khaled Ahmed, Philip Kraus
  • Patent number: 7179754
    Abstract: A method and apparatus for forming a nitrided gate dielectric layer. The method includes generating a nitrogen-containing plasma in a processing chamber via a smooth-varying modulated RF power source to reduce electron temperature spike. Field effect transistor channel mobility and gate leakage current results are improved when the power source is smooth-varying modulated, as compared to square-wave modulated.
    Type: Grant
    Filed: April 6, 2004
    Date of Patent: February 20, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Philip A. Kraus, Thai Cheng Chua
  • Publication number: 20070010103
    Abstract: A method of forming a silicon oxynitride gate dielectric. The method includes providing a structure comprising a silicon film formed on a substrate. The structure is exposed to a first plasma comprising a nitrogen source to incorporate nitrogen into the silicon film. The structure is oxidized in an atmosphere comprising nitric oxide to form a silicon oxynitride gate dielectric on the structure. The structure is then exposed to a second plasma comprising a nitrogen source.
    Type: Application
    Filed: July 11, 2005
    Publication date: January 11, 2007
    Inventors: Thai Chua, Christopher Olsen, Philip Kraus, Khaled Ahmed, Cory Czarnik
  • Publication number: 20060216944
    Abstract: A method and apparatus for forming a nitrided gate dielectric layer. The method includes generating a nitrogen-containing plasma in a processing chamber via a smooth-varying modulated RF power source to reduce electron temperature spike. Field effect transistor channel mobility and gate leakage current results are improved when the power source is smooth-varying modulated, as compared to square-wave modulated.
    Type: Application
    Filed: May 31, 2006
    Publication date: September 28, 2006
    Inventors: Philip Kraus, Thai Chua
  • Publication number: 20060153995
    Abstract: Methods for forming dielectric materials on a substrate in a single cluster tool are provided. In one embodiment, the method includes providing a cluster tool having a plurality of deposition chambers, depositing a metal-containing oxide layer on a substrate in a first chamber of the cluster tool, treating the metal-containing oxide layer with an insert plasma process in a second chamber of the cluster tool, annealing the metal-containing oxide layer in a third chamber of the cluster tool, and depositing a gate electrode layer on the annealed substrate in a fourth chamber of the cluster tool.
    Type: Application
    Filed: December 9, 2005
    Publication date: July 13, 2006
    Inventors: Pravin Narwankar, Shreyas Kher, Shankar Muthukrishnan, Rahul Sharangpani, Philip Kraus, Chris Olsen, Khaled Ahmed
  • Publication number: 20050260357
    Abstract: In one embodiment, a method for forming a dielectric stack on a substrate is provided which includes depositing a first layer of a dielectric material on a substrate surface, exposing the first layer to a nitridation process, depositing a second layer of the dielectric material on the first layer, exposing the second layer to the nitridation process, and exposing the substrate to an anneal process. In another embodiment, a method for forming a dielectric material on a substrate is provided which includes depositing a metal oxide layer substantially free of silicon on a substrate surface, exposing the metal oxide layer to a nitridation process, and exposing the substrate to an anneal process.
    Type: Application
    Filed: May 21, 2004
    Publication date: November 24, 2005
    Inventors: Christopher Olsen, Pravin Narwankar, Shreyas Kher, Randhir Thakur, Shankar Muthukrishnan, Philip Kraus
  • Publication number: 20040242021
    Abstract: A method and apparatus for forming a nitrided gate dielectric layer. The method includes generating a nitrogen-containing plasma in a processing chamber via a smooth-varying modulated RF power source to reduce electron temperature spike. Field effect transistor channel mobility and gate leakage current results are improved when the power source is smooth-varying modulated, as compared to square-wave modulated.
    Type: Application
    Filed: April 6, 2004
    Publication date: December 2, 2004
    Applicant: Applied Materials, Inc.
    Inventors: Philip A. Kraus, Thai Cheng Chua