Abstract: Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.

Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.

Abstract: Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.

Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.

Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.

Abstract: Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.

Abstract: Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.

Abstract: A method of forming a semiconductor device for improving an electrical connection. The semiconductor device includes a top metal layer. A protective dielectric layer is formed over the top metal layer. A sintering operation is performed while the top metal layer is covered by the protective dielectric layer. After the sintering operation, the protective dielectric layer is patterned to expose areas on the top metal layer for bond pads of the semiconductor device. A bond pad cap is formed on the top metal layer where exposed by the protective dielectric layer.

Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.

Abstract: Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.

Abstract: Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.

Abstract: A die and method for extruding an extrudable material to form an extruded member is described. In one embodiment, the die comprises a barrier member comprising a plurality of feed channels that extend through the barrier member. Furthermore, the die incorporates a passage forming member extending from the barrier member substantially in the direction of extrusion. The feed channels are arranged with respect to the passage forming member to allow the extrudable material to substantially flow about the passage forming member to form a corresponding passage in the extruded member.

Abstract: Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.

Abstract: An electronic device is formed by providing a substrate having a recess at a top surface. A layer of an organic protective material is formed over the substrate, with the organic protective material extending into the recess. A polishing process is performed on the layer of protective material. The polishing process may remove a portion of an underlying metal layer over the top surface while protecting the underlying metal layer within the recess.

Abstract: A microelectronic device is formed by providing a substrate having a recess at a top surface, and a liner layer formed over the top surface of the substrate, extending into the recess. A protective layer is formed over the liner layer, extending into the recess. A CMP process removes the protective layer and the liner layer from over the top surface of the substrate, leaving the protective layer and the liner layer in the recess. The protective layer is subsequently removed from the recess, leaving the liner layer in the recess. The substrate may include an interconnect region with a bond pad and a PO layer having an opening which forms the recess; the bond pad is exposed in the recess. The liner layer in the recess may be a metal liner suitable for a subsequently-formed wire bond or bump bond.

Abstract: A microelectronic device is formed by providing a substrate having a recess at a top surface, and a liner layer formed over the top surface of the substrate, extending into the recess. A protective layer is formed over the liner layer, extending into the recess. A CMP process removes the protective layer and the liner layer from over the top surface of the substrate, leaving the protective layer and the liner layer in the recess. The protective layer is subsequently removed from the recess, leaving the liner layer in the recess. The substrate may include an interconnect region with a bond pad and a PO layer having an opening which forms the recess; the bond pad is exposed in the recess. The liner layer in the recess may be a metal liner suitable for a subsequently-formed wire bond or bump bond.

Abstract: A microelectronic device is formed by providing a substrate having a recess at a top surface, and a liner layer formed over the top surface of the substrate, extending into the recess. A protective layer is formed over the liner layer, extending into the recess. A CMP process removes the protective layer and the liner layer from over the top surface of the substrate, leaving the protective layer and the liner layer in the recess. The protective layer is subsequently removed from the recess, leaving the liner layer in the recess. The substrate may include an interconnect region with a bond pad and a PO layer having an opening which forms the recess; the bond pad is exposed in the recess. The liner layer in the recess may be a metal liner suitable for a subsequently-formed wire bond or bump bond.

Abstract: A microelectronic device is formed by providing a substrate having a recess at a top surface, and a liner layer formed over the top surface of the substrate, extending into the recess. A protective layer is formed over the liner layer, extending into the recess. A CMP process removes the protective layer and the liner layer from over the top surface of the substrate, leaving the protective layer and the liner layer in the recess. The protective layer is subsequently removed from the recess, leaving the liner layer in the recess. The substrate may include an interconnect region with a bond pad and a PO layer having an opening which forms the recess; the bond pad is exposed in the recess. The liner layer in the recess may be a metal liner suitable for a subsequently-formed wire bond or bump bond.

Abstract: Systems, methods, apparatuses, and software for providing enhanced measurement and correction of physiological data are provided herein. In a first example, a physiological measurement system is configured to obtain a measured photoplethysmogram (PPG) for a patient, and obtain a reference signal for the patient measured concurrent with the measured PPG, the reference signal including noise components related to at least motion of the patient. The physiological measurement system also is configured to determine a filtered PPG from the measured PPG using at least an adaptive filter with the reference signal to reduce noise components of the measured PPG, determine a final PPG by spectrally subtracting at least a portion of the noise components of the reference signal from the filtered PPG, and identify one or more physiological metrics of the patient based on the final PPG.

Abstract: Systems, methods, sensors, and software for providing enhanced measurement and correction of physiological data are provided herein. In one example, a capacitive sensor of a measurement system is positioned onto tissue of a patient. The capacitive sensor includes one or more conductive elements with associated gain properties that are positioned near optical sensor elements proximate to the tissue of the patient, the optical sensor elements positioned to measure a photoplethysmogram (PPG) for the tissue. The measurement system drives the capacitive sensor and measures capacitance signals associated with the capacitance sensor. The measurement system corrects for at least motion noise in the PPG using the capacitance signals.