Patents by Inventor Philip Davis

Philip Davis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250116788
    Abstract: A method of processing a counting output associated with a counting device comprising: (i) calculating a first time-to-count average value based on time-to-count values obtained for a number of events ‘n’ between events x1 and xn; (ii) measuring a time-to-count value associated with event xn+1; and (iii) calculating a second time-to-count average value based on time-to-count values obtained for the number of events ‘n’ between events x2 and xn+1.
    Type: Application
    Filed: December 7, 2022
    Publication date: April 10, 2025
    Applicant: Tracerco Limited
    Inventors: Philip Davies, David James Fitzgerald, Andrew James O'Malley, Claire Watson
  • Publication number: 20250110246
    Abstract: A radiation detection apparatus (210) comprises a Geiger-Müller tube (220) comprising a chamber (222) equipped with an anode (230) and a cathode (240); a first connection configured to connect the anode (230) to an anode activation potential; and a second connection configured to connect the cathode (240) to a cathode activation potential, wherein the first connection comprises or consists of a permanent connection to a voltage supply (270). The apparatus comprises a transistor (281) configured to temporarily connect the cathode to its activation potential.
    Type: Application
    Filed: December 6, 2022
    Publication date: April 3, 2025
    Applicant: Tracerco Limited
    Inventors: Philip Davies, Robert Holloway
  • Patent number: 12204323
    Abstract: The systems and methods disclosed herein enable mapping of gaps in controls to operative standards. The system receives an output generation request using an artificial intelligence (AI) model, where the input includes a set of gaps associated with one or more scenarios failing to satisfy the operative standards of a set of vector representations. Each gap in the set of gaps includes attributes defining the scenario. Using the received input, the system constructs prompts for each gap, where the prompts include information related to the scenario and/or the operative standards. Each prompt compares the corresponding gap against the operative standards or the set of vector representations. For each gap, the system maps the gap to the operative standards by supplying the prompt of the particular gap into the AI model and, in response, receiving from the AI model the operative standards associated with the particular gap.
    Type: Grant
    Filed: July 12, 2024
    Date of Patent: January 21, 2025
    Inventors: Shardul Malviya, Samantha Cory, Mariusz Saternus, Daniel Lewandowski, Biraj Krushna Rath, Stuart Murray, Philip Davies, Payal Jain, Tariq Husayn Maonah
  • Patent number: 12197859
    Abstract: The systems and methods disclosed herein receive an output generation request from that includes input for generating an output using a language model. The input includes a set of alphanumeric characters associated with operative standards for a first set of actions. The system divides the set of alphanumeric characters into text subsets. For each text subset, a vector representation is determined. Prompts are created for each vector representation including the set of alphanumeric characters, query contexts, keywords, and/or the text subset. Each vector representation's prompt is input into the language model, which generates a second set of actions of related actions, where subsequently generated actions are based on prior generated actions. The system aggregates the second set of actions into a third set of actions and displays a graphical layout. The graphical layout displays a representation of the set of alphanumeric characters and the corresponding actions.
    Type: Grant
    Filed: July 23, 2024
    Date of Patent: January 14, 2025
    Assignee: CITIBANK, N.A.
    Inventors: Shardul Malviya, Wayne Liao, Deepak Jain, Samantha Cory, Mariusz Saternus, Daniel Lewandowski, Biraj Krushna Rath, Stuart Murray, Philip Davies, Payal Jain, Tariq Husayn Maonah
  • Patent number: 12159846
    Abstract: A method of forming a semiconductor device for improving an electrical connection. The semiconductor device includes a top metal layer. A protective dielectric layer is formed over the top metal layer. A sintering operation is performed while the top metal layer is covered by the protective dielectric layer. After the sintering operation, the protective dielectric layer is patterned to expose areas on the top metal layer for bond pads of the semiconductor device. A bond pad cap is formed on the top metal layer where exposed by the protective dielectric layer.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: December 3, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Richard Allen Faust, Robert Martin Higgins, Anagha Shashishekhar Kulkarni, Jonathan Philip Davis, Sudtida Lavangkul, Andrew Frank Burnett
  • Patent number: 12147513
    Abstract: The systems and methods disclosed herein relate to a model validation platform that enables dynamic validation of a user's prompt for a large language model (LLM) in order to evaluate the validity of the prompt and the suitability of a large language model for processing the prompt. For example, the platform enables an estimation of the resource allocation associated with processing the prompt with a given LLM, as well as a modification of the prompt, prior to the processing the prompt with the selected LLM. The platform can further validate the output prior to transmitting the output to a server system for display to the user. By doing so, the platform enables dynamic evaluation of a request to execute an LLM, as well as evaluation of resulting outputs, for accuracy and efficiency improvements in data processing or software development pipelines.
    Type: Grant
    Filed: April 11, 2024
    Date of Patent: November 19, 2024
    Assignee: Citibank, N.A.
    Inventors: Payal Jain, Tariq Husayn Maonah, Mariusz Saternus, Daniel Lewandowski, Biraj Krushna Rath, Stuart Murray, Philip Davies
  • Patent number: 12111747
    Abstract: The systems and methods disclosed herein enable evaluation of machine learning model outputs within a virtual environment. The disclosed model validation platform enables testing of code generated for detection of malicious or anomalous outputs. For example, the model validation platform can construct a virtual machine isolated from the system and test model-generated code for validation of LLM-generated outputs. In some implementations, the model validation platform determines parameters of the virtual machine and/or associated validation test based on an evaluation of the machine learning model's output and/or the associated underlying prompt. For example, the parameters of the validation test depend on an evaluation of the user or the provided input (e.g., depending on the presence of sensitive data within the prompt). By doing so, the system enables dynamic evaluation of machine learning model outputs to improve the security and robustness of associated generated code.
    Type: Grant
    Filed: May 10, 2024
    Date of Patent: October 8, 2024
    Assignee: CITIBANK, N.A.
    Inventors: Payal Jain, Tariq Husayn Maonah, Mariusz Saternus, Daniel Lewandowski, Biraj Krushna Rath, Stuart Murray, Philip Davies
  • Patent number: 12106205
    Abstract: The disclosed data generation platform enables selection of particular machine learning models on the basis of a predicted resource allocation requirement associated with a given prompt. For example, the model validation platform can evaluate the resource use (e.g., cost) associated with processing a user's prompt with a given type of model. Based on this estimated resource use, the model validation platform can route the prompt to a suitable model to optimize a performance metric value, thereby improving the efficiency of the system. In some implementations, the data generation platform trains a model to accurately estimate resource usage based on ground-truth model-related costs, thereby improving the effectiveness of model selection for efficiency improvements.
    Type: Grant
    Filed: May 10, 2024
    Date of Patent: October 1, 2024
    Assignee: CITIBANK, N.A.
    Inventors: Payal Jain, Tariq Husayn Maonah, Mariusz Saternus, Daniel Lewandowski, Biraj Krushna Rath, Stuart Murray, Philip Davies
  • Publication number: 20240105501
    Abstract: Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.
    Type: Application
    Filed: December 6, 2023
    Publication date: March 28, 2024
    Inventors: Karen Hildegard Ralston Kirmse, Jonathan Philip Davis
  • Patent number: 11916067
    Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: February 27, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Robert M. Higgins, Henry Litzmann Edwards, Xiaoju Wu, Shariq Arshad, Li Wang, Jonathan Philip Davis, Tathagata Chatterjee
  • Patent number: 11908729
    Abstract: Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: February 20, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Karen Hildegard Ralston Kirmse, Jonathan Philip Davis
  • Publication number: 20230406730
    Abstract: A desalination system and a method for operating the desalination system. An example desalination system includes a partitioned container, a membrane container housing a cross-flow semipermeable membrane, a feed pump for supplying saline water, a recirculation pump, a main valve, a bypass valve and a purge valve. The system operates in a first pressurisation stage where saline water is provided by the feed pump while the bypass valve is open, followed by a second pressurisation stage where an upstream compartment of the container is filled and a recharge stage where the main valve is closed and concentrated saline water is purged via the purge valve. An inlet valve may be provided, which is closed in the first pressurisation stage and open in the second pressurisation stage and recharge stage.
    Type: Application
    Filed: November 5, 2021
    Publication date: December 21, 2023
    Inventors: Philip Davies, Timothy Naughton, Liam Burlace, Kiho Park
  • Patent number: 11539612
    Abstract: According to a first aspect, there is provided a method of testing a plurality of virtual network functions (VNFs) during commissioning of the plurality of VNFs in a virtualized environment in a customer network, the method comprising: at a VNF testing component configured to have access to the virtualized environment of the customer network, performing interoperability testing between a first VNF component instantiation (VNFCI) within a first VNF of the plurality of VNFs and a second VNFCI within a second VNF of the plurality of VNFs, the second VNF being different from the first VNF, the first VNF and the second VNF comprising a subset of VNFs within the plurality of VNFs, wherein performing the interoperability testing comprises: instructing the first VNFCI to interoperate directly with the second VNFCI in a predetermined manner; and determining whether the second VNFCI reacts to the instructed direct interoperation in an expected manner.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: December 27, 2022
    Assignee: Metaswitch Networks Ltd
    Inventors: Andrew Lee, David Hotham, Joe Powell, Philip Davies, Michael Duppre, Jamie Parsons, Steve Orbell
  • Patent number: 11431262
    Abstract: A system (10) for converting power comprising a plurality of modules (14) connected in series and having each at least one DC power source. Storage devices (18) are provided with each module (14) to store power from the power source and voltage control circuitry (19) in each module (14) connects the storage device between a maximum module voltage, a minimum module voltage to create a stepwise approximation of a mains signal. A compensator unit (20) is provided in series with the modules (14) including a storage device charged by the power sources. While each of the modules (14) is supplying either its maximum or minimum voltage to the system a control unit ramps up or down the voltage between the input and output of the compensator unit (20) to follow the desired AC signal.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: August 30, 2022
    Inventors: Kevin Stephen Davies, Alexander Philip Davies
  • Patent number: 11425203
    Abstract: Certain aspects provide a method of commissioning a virtualized network function (VNF), including: at a commissioning virtual machine instantiated in a virtualized environment of a customer network, configuring a remote access connection facility for accessing the commissioning virtual machine remotely from outside of the customer network, wherein the commissioning virtual machine has access to a virtual infrastructure manager (VIM) component of the virtualized environment; causing, via the remote access connection facility, configuration of a VNF manager component within the commissioning virtual machine; and causing, via the remote access connection facility, the configured VNF manager component to instruct the VIM component to instantiate one or more virtual machines in the virtualized environment, the one or more virtual machines being operable to perform at least a part of the VNF.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: August 23, 2022
    Assignee: METASWITCH NETWORKS LTD
    Inventors: Andrew Lee, David Hotham, Joe Powell, Philip Davies, Michael Duppre, Jamie Parsons, Steve Orbell
  • Publication number: 20220189949
    Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.
    Type: Application
    Filed: March 2, 2022
    Publication date: June 16, 2022
    Inventors: Robert M. Higgins, Henry Litzmann Edwards, Xiaoju Wu, Shariq Arshad, Li Wang, Jonathan Philip Davis, Tathagata Chatterjee
  • Patent number: 11296075
    Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: April 5, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Robert M. Higgins, Henry Litzmann Edwards, Xiaoju Wu, Shariq Arshad, Li Wang, Jonathan Philip Davis, Tathagata Chatterjee
  • Publication number: 20220005729
    Abstract: Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.
    Type: Application
    Filed: September 17, 2021
    Publication date: January 6, 2022
    Inventors: Karen Hildegard Ralston Kirmse, Jonathan Philip Davis
  • Patent number: 11171035
    Abstract: Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: November 9, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Karen Hildegard Ralston Kirmse, Jonathan Philip Davis
  • Patent number: 11076978
    Abstract: A controlled discharge ostomy appliance assembly comprises (i) a stoma seal that is self-urging with a dynamic damping characteristic that resists changes of seal volume, (ii) a press-fit coupling member displaceable from an unlocked position to a locked position as part of a press-fit process, and (iii) a single-use frangible portion. The assembly further includes a protector shield removably fastened to the appliance forming a combined assembly therewith. The protector shield comprises (i) a seal displacer manipulable for displacing the stoma seal to a non-operative position ready for fitting, (ii) a substantially rigid coupling member guard portion for protecting the state of the coupling member, and (iii) a bracing portion for bracing the single-use frangible portion.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: August 3, 2021
    Assignee: CONVATEC TECHNOLOGIES INC.
    Inventors: Tinh Nguyen-Demary, John Cline, John Blum, Gary Stacey, Philip Davies, Trevor Beckett