Patents by Inventor Philip Davis
Philip Davis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220189949Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.Type: ApplicationFiled: March 2, 2022Publication date: June 16, 2022Inventors: Robert M. Higgins, Henry Litzmann Edwards, Xiaoju Wu, Shariq Arshad, Li Wang, Jonathan Philip Davis, Tathagata Chatterjee
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Patent number: 11296075Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.Type: GrantFiled: August 31, 2018Date of Patent: April 5, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Robert M. Higgins, Henry Litzmann Edwards, Xiaoju Wu, Shariq Arshad, Li Wang, Jonathan Philip Davis, Tathagata Chatterjee
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Publication number: 20220005729Abstract: Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.Type: ApplicationFiled: September 17, 2021Publication date: January 6, 2022Inventors: Karen Hildegard Ralston Kirmse, Jonathan Philip Davis
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Patent number: 11171035Abstract: Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.Type: GrantFiled: September 11, 2019Date of Patent: November 9, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Karen Hildegard Ralston Kirmse, Jonathan Philip Davis
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Patent number: 11076978Abstract: A controlled discharge ostomy appliance assembly comprises (i) a stoma seal that is self-urging with a dynamic damping characteristic that resists changes of seal volume, (ii) a press-fit coupling member displaceable from an unlocked position to a locked position as part of a press-fit process, and (iii) a single-use frangible portion. The assembly further includes a protector shield removably fastened to the appliance forming a combined assembly therewith. The protector shield comprises (i) a seal displacer manipulable for displacing the stoma seal to a non-operative position ready for fitting, (ii) a substantially rigid coupling member guard portion for protecting the state of the coupling member, and (iii) a bracing portion for bracing the single-use frangible portion.Type: GrantFiled: April 16, 2018Date of Patent: August 3, 2021Assignee: CONVATEC TECHNOLOGIES INC.Inventors: Tinh Nguyen-Demary, John Cline, John Blum, Gary Stacey, Philip Davies, Trevor Beckett
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Publication number: 20210005560Abstract: A method of forming a semiconductor device for improving an electrical connection. The semiconductor device includes a top metal layer. A protective dielectric layer is formed over the top metal layer. A sintering operation is performed while the top metal layer is covered by the protective dielectric layer. After the sintering operation, the protective dielectric layer is patterned to expose areas on the top metal layer for bond pads of the semiconductor device. A bond pad cap is formed on the top metal layer where exposed by the protective dielectric layer.Type: ApplicationFiled: December 9, 2019Publication date: January 7, 2021Applicant: Texas Instruments IncorporatedInventors: Richard Allen Faust, Robert Martin Higgins, Anagha Shashishekhar Kulkarni, Jonathan Philip Davis, Sudtida Lavangkul, Andrew Frank Burnett
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Publication number: 20200344144Abstract: According to a first aspect, there is provided a method of testing a plurality of virtual network functions (VNFs) during commissioning of the plurality of VNFs in a virtualized environment in a customer network, the method comprising: at a VNF testing component configured to have access to the virtualized environment of the customer network, performing interoperability testing between a first VNF component instantiation (VNFCI) within a first VNF of the plurality of VNFs and a second VNFCI within a second VNF of the plurality of VNFs, the second VNF being different from the first VNF, the first VNF and the second VNF comprising a subset of VNFs within the plurality of VNFs, wherein performing the interoperability testing comprises: instructing the first VNFCI to interoperate directly with the second VNFCI in a predetermined manner; and determining whether the second VNFCI reacts to the instructed direct interoperation in an expected manner.Type: ApplicationFiled: April 16, 2020Publication date: October 29, 2020Inventors: Andrew Lee, David Hotham, Joe Powell, Philip Davies, Michael Duppre, Jamie Parsons, Steve Orbell
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Patent number: 10669499Abstract: In some embodiments, a compound has the formula (I) where: R1 and R2 are alkyl or, together with the carbon atom to which they are attached, cycloalkyl; R3, R4 and R5 are H or alkyl (formula II); R6 is alkyl or where: R7 and R8 are H, alkyl or, together with the carbon atom to which they are attached, cycloalkyl; R9 is H or alkyl; X is alkylene or is absent; and p is 0, 1, 2 or 3; and m and n are 0, 1, 2 or 3 provided that m is 0 when R4 and R5 are H. The compound is suitable for use as a base stock which provides low volatility for a given viscosity profile. The compound may be used in a lubricant composition for an internal combustion engine.Type: GrantFiled: June 17, 2016Date of Patent: June 2, 2020Inventors: Gordon Lamb, Amit Gokhale, John Philip Davies, John Redshaw, Peter Seden, Kevin West
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Publication number: 20200075583Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.Type: ApplicationFiled: August 31, 2018Publication date: March 5, 2020Inventors: Robert M. Higgins, Henry Litzmann Edwards, Xiaoju Wu, Shariq Arshad, Li Wang, Jonathan Philip Davis, Tathagata Chatterjee
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Publication number: 20200006118Abstract: Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.Type: ApplicationFiled: September 11, 2019Publication date: January 2, 2020Inventors: Karen Hildegard Ralston Kirmse, Jonathan Philip Davis
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Patent number: 10453738Abstract: Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.Type: GrantFiled: December 22, 2017Date of Patent: October 22, 2019Assignee: Texas Instruments IncorporatedInventors: Karen Hildegard Ralston Kirmse, Jonathan Philip Davis
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Publication number: 20190198382Abstract: Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.Type: ApplicationFiled: December 22, 2017Publication date: June 27, 2019Inventors: Karen Hildegard Ralston Kirmse, Jonathan Philip Davis
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Patent number: 10222087Abstract: The present invention relates to a system and method of cooling by latent energy transfer and, in particular, to cool a fluid by discharging unwanted low temperature thermal energy to a surrounding ambient environment utilizing a fluid evaporation process involving permitted or forced ventilation of air across a surface area of a heat transfer fluid. The invention further relates to an air treatment system utilizing the cooled heat transfer fluid for cooling air and for supplying ventilation air to the evaporation process. A body of liquid is cooled close to the prevailing wet bulb temperature, discharging unwanted thermal energy to the surroundings, rendering the liquid suitable as a cooling medium for removing unwanted thermal energy from a location or in a process.Type: GrantFiled: October 27, 2015Date of Patent: March 5, 2019Assignee: Intex Holdings Pty LtdInventor: Roger Philip Davies
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Patent number: 10203133Abstract: The present invention relates to a solar energy collection apparatus and design method. In particular, the invention provides a solar energy collection apparatus incorporating one or more reflectors and a solar collector for receiving incoming solar radiation, including reflected radiation from the one or more reflectors, wherein the one or more reflectors and the collector are oriented according to a pre-calculated offset length and offset angle based at least on the latitude of the apparatus. The invention further provides a computer-implemented method of designing a solar collection apparatus including determining the optimal offset length and offset angle between the one or more reflectors and the collector for a given latitude and other inputs.Type: GrantFiled: May 23, 2014Date of Patent: February 12, 2019Assignee: Intex Holdings Pty LtdInventor: Roger Philip Davies
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Patent number: 10184675Abstract: The present invention relates to a dehumidification system and method and, in particular, to a system and method for controlling the humidity of air in a process or location using a desiccant-coated fluid-air heat exchanger. The desiccant material adsorbs water at or above ambient temperatures during an adsorption cycle, and the resultant air stream is of a reduced humidity compared with the humidity of the supply air. The desiccant material may then be dried during a regeneration cycle through addition of heating fluid through the heat exchanger, driving water back into the vapor state with addition of latent energy of vaporization. The desiccant material may be cooled, during the adsorption cycle, through addition of cooling fluid through the heat exchanger to maintain the temperature within a range sufficient for water vapor to be removed from the stream of air.Type: GrantFiled: October 27, 2015Date of Patent: January 22, 2019Assignee: Intex Holdings Pty LtdInventor: Roger Philip Davies
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Publication number: 20190006299Abstract: An electronic device is formed by providing a substrate having a recess at a top surface. A layer of an organic protective material is formed over the substrate, with the organic protective material extending into the recess. A polishing process is performed on the layer of protective material. The polishing process may remove a portion of an underlying metal layer over the top surface while protecting the underlying metal layer within the recess.Type: ApplicationFiled: September 5, 2018Publication date: January 3, 2019Inventors: Jonathan Philip Davis, Andrew Frank Burnett, Brian Edward Zinn
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Patent number: 10135362Abstract: Described is a method for converting power including controlling operation of a plurality of series connected modules including a DC power sources and storage devices such that the total voltage across the series connected modules includes an AC signal. A storage parameter is defined based on a sum of a function of the voltages in the storage devices in the modules and one or more voltage control levels are defined for each of or a plurality of the storage devices. An average current drawn from the series connected modules over a time period is set such that the storage parameter approaches a target value. The target value is decreased for a subsequent time period in the event that none the voltage control levels are reached and increased in the event that one or more of the voltage control levels are reached.Type: GrantFiled: July 1, 2015Date of Patent: November 20, 2018Inventors: Alexander Philip Davies, Kevin Stephen Davies
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Patent number: 10125335Abstract: A lubricating composition comprising a base oil of lubricating viscosity and one or more lubricant additives, wherein the base oil comprises or consists of a base stock which comprises or consists of at least one isoprenoid compound comprising: (i) one or two oxygen-containing moieties independently selected from ether and ester moieties; (ii) a first acyclic isoprenoid moiety containing 1 to 5 isoprenyl units; and (iii) optionally, a second acyclic isoprenoid moiety containing 1 to 5 isoprenyl units with the proviso that at least one isoprenoid moiety contains 3 to 5 isoprenyl units where the isoprenoid compound contains a single ether moiety.Type: GrantFiled: June 27, 2014Date of Patent: November 13, 2018Assignee: CASTROL LIMITEDInventors: Martin E. Carrera, John Philip Davies, Sander Gaemers, John William Shabaker, Oliver Williams
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Patent number: 10090264Abstract: A microelectronic device is formed by providing a substrate having a recess at a top surface, and a liner layer formed over the top surface of the substrate, extending into the recess. A protective layer is formed over the liner layer, extending into the recess. A CMP process removes the protective layer and the liner layer from over the top surface of the substrate, leaving the protective layer and the liner layer in the recess. The protective layer is subsequently removed from the recess, leaving the liner layer in the recess. The substrate may include an interconnect region with a bond pad and a PO layer having an opening which forms the recess; the bond pad is exposed in the recess. The liner layer in the recess may be a metal liner suitable for a subsequently-formed wire bond or bump bond.Type: GrantFiled: February 16, 2017Date of Patent: October 2, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jonathan Philip Davis, Andrew Frank Burnett, Brian Edward Zinn
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Publication number: 20180235802Abstract: A controlled discharge ostomy appliance assembly comprises (i) a stoma seal that is self-urging with a dynamic damping characteristic that resists changes of seal volume, (ii) a press-fit coupling member displaceable from an unlocked position to a locked position as part of a press-fit process, and (iii) a single-use frangible portion. The assembly further includes a protector shield removably fastened to the appliance forming a combined assembly therewith. The protector shield comprises (i) a seal displacer manipulable for displacing the stoma seal to a non-operative position ready for fitting, (ii) a substantially rigid coupling member guard portion for protecting the state of the coupling member, and (iii) a bracing portion for bracing the single-use frangible portion.Type: ApplicationFiled: April 16, 2018Publication date: August 23, 2018Inventors: Tinh Nguyen-Demary, John Cline, John Blum, Gary Stacey, Philip Davies, Trevor Beckett