Patents by Inventor Philip J. Kuekes

Philip J. Kuekes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110266605
    Abstract: A memory device (100) includes a semiconductor wire including a source region (132), a drain region (134), and a channel region (130) between the source region (132) and the drain region (134). A gate structure that overlies the channel region includes a memristive portion (120) and a conductive portion (110) overlying the memristive portion (120).
    Type: Application
    Filed: January 30, 2009
    Publication date: November 3, 2011
    Inventors: Dmitri B. Strukov, Philip J. Kuekes, Duncan Stewart, Zhiyong Li
  • Publication number: 20110266510
    Abstract: Various embodiments of the present invention are direct to nanoscale, reconfigurable memristor devices. In one aspect, a memristor device (500,600) comprises an active region (508,610) sandwiched between a first electrode (301) and a second electrode (302).
    Type: Application
    Filed: January 26, 2009
    Publication date: November 3, 2011
    Inventors: Nathaniel J. Quitoriano, Philip J. Kuekes, Jianhua Yang
  • Patent number: 8045253
    Abstract: Various embodiments of the present invention are directed to systems and methods for obtaining images of objects with higher resolution than the diffraction limit. In one aspect, a method for collecting evanescent waves scattered from an object comprises electronically configuring a reconfigurable device to operate as a grating for one or more lattice periods using a computing device. Propagating waves scattered from the object pass through the reconfigurable device and a portion of evanescent waves scattered from the object are projected into the far field of the object. The method includes detecting propagating waves and detecting the portion of evanescent waves projected into the far field for each lattice period using an imaging system.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: October 25, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jingjing Li, Philip J. Kuekes
  • Publication number: 20110248381
    Abstract: A multilayer memristive device includes a first electrode (410); a second electrode (405); a first memristive region (430) and a second memristive region (435) which created by directional ion implantation of dopant ions (420, 425) and are interposed between the first electrode (410) and the second electrode (405); and mobile dopants (315) which move within the first memristive region (430) and the second memristive region (435) in response to an applied electrical field.
    Type: Application
    Filed: January 20, 2009
    Publication date: October 13, 2011
    Inventors: William Tong, Nathaniel J. Quitoriano, Duncan Stewart, Philip J. Kuekes
  • Publication number: 20110249322
    Abstract: Nanowire-based opto-electronic devices including nanowire lasers, photodetectors and semiconductor optical amplifiers are disclosed. The devices include nanowires grown from single crystal and/or non-single surfaces. The semiconductor optical amplifiers include nanowire arrays that act as ballast lasers to amplify a signal carried by a signal waveguide. Embodiments of the nanowire lasers and photodetectors include horizontal and vertical nanowires that can provide different polarizations.
    Type: Application
    Filed: April 25, 2007
    Publication date: October 13, 2011
    Inventors: Shih-Yuan Wang, M. Saif Islam, Philip J. Kuekes, Nobuhiko Kobayashi
  • Publication number: 20110221027
    Abstract: Various embodiments of the present invention are direct to nanoscale, reconfigurable, memristor devices. In one aspect, a memristor device comprises an electrode (301,303) and an alloy electrode (502,602). The device also includes an active region (510,610) sandwiched between the electrode and the alloy electrode. The alloy electrode forms dopants in a sub-region of the active region adjacent to the alloy electrode. The active region can be operated by selectively positioning the dopants within the active region to control the flow of charge carriers between the electrode and the alloy electrode.
    Type: Application
    Filed: January 26, 2009
    Publication date: September 15, 2011
    Inventors: Nathaniel J. Quitoriano, Douglas Ohlberg, Philip J. Kuekes, Jianhua Yang
  • Patent number: 8004876
    Abstract: A computing system for implementing at least one electronic circuit with gain comprises at least one two-dimensional molecular switch array. The molecular switch array is formed by assembling two or more crossed planes of wires into a configuration of devices. Each device comprises a junction formed by a pair of crossed wires and at least one connector species that connects the pair of crossed wires in the junction. The junction has a functional dimension in nanometers, and includes a switching capability provided by both (1) one or more connector species and the pair of crossed wires and (2) a configurable nano-scale wire transistor having a first state that functions as a transistor and a second state that functions as a conducting semiconductor wire. Specific connections are made to interconnect the devices and connect the devices to two structures that provide high and low voltages.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: August 23, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Gregory S. Snider, Philip J. Kuekes, R. Stanley Williams
  • Patent number: 7989798
    Abstract: A patterned array of metallic nanostructures and fabrication thereof is described. A device comprises a patterned array of metallic columns vertically extending from a substrate. Each metallic column is formed by metallically coating one of an array of non-metallic nanowires catalytically grown from the substrate upon a predetermined lateral pattern of seed points placed thereon according to a nanoimprinting process. An apparatus for fabricating a patterned array of metallic nanostructures is also described.
    Type: Grant
    Filed: July 27, 2009
    Date of Patent: August 2, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Philip J Kuekes, M. Saif Islam, Shih-Yuan Wang, Alexandre M. Bratkovski
  • Publication number: 20110181307
    Abstract: In one embodiment of the present invention, a microscale or sub-microscale signal line, interconnected with one set of parallel nanowires of a nanowire crossbar, serves as a multiplexer. The multiplexer is used to detect the conductivity state of a nanowire junction within the nanowire crossbar. In one method embodiment of the present invention, a first signal is output to the two nanowires interconnected by the nanowire junction, while a second signal is output to the remaining nanowires of the nanowire crossbar. Then, the second signal is output to the two nanowires interconnected by the nanowire junction, while the first signal is output to the remaining nanowires of the nanowire crossbar. The resulting signal detected on the multiplexer is reflective of the conductivity state of the nanowire junction.
    Type: Application
    Filed: March 5, 2009
    Publication date: July 28, 2011
    Inventor: Philip J. Kuekes
  • Patent number: 7983519
    Abstract: A photonic connection includes a first fiber and a second fiber. The first fiber has a core with a first predetermined pattern defined on or in a facet thereof, and the second fiber has a core with a second predetermined pattern defined on or in a facet thereof. The second predetermined pattern is complementary to the first predetermined pattern such that the first fiber or the second fiber fits into another of the second fiber or the first fiber at a single orientation and position.
    Type: Grant
    Filed: October 16, 2008
    Date of Patent: July 19, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Theodore I. Kamins, Wei Wu, Shih-Yuan Wang, Philip J Kuekes, Michael Tan
  • Publication number: 20110173306
    Abstract: The invention is a system and method for reconfigurable computers. The invention involves a plurality of reconfigurable component clusters (RCCs), each of which can change their respective configuration upon receiving a configuration command. The invention uses a reconfiguration network for distributing the configuration command to the RCCs, wherein the reconfiguration network comprises a plurality of cells, wherein each RCC is connected to a cell.
    Type: Application
    Filed: March 22, 2011
    Publication date: July 14, 2011
    Inventors: Michael S. Schlansker, Boon Seong Ang, Philip J. Kuekes
  • Patent number: 7975068
    Abstract: The invention is a system and method for reconfigurable computers. The invention involves a plurality of reconfigurable component clusters (RCCs), each of which can change their respective configuration upon receiving a configuration command. The invention uses a reconfiguration network for distributing the configuration command to the RCCs, wherein the reconfiguration network comprises a plurality of cells, wherein each RCC is connected to a cell.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: July 5, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Michael S. Schlansker, Boon Seong Ang, Philip J. Kuekes
  • Patent number: 7948271
    Abstract: A programmable logic array (PLA) comprising a two-dimensional array of a plurality of nanometer-scale switches is provided. Each switch comprises a pair of crossed wires which form a junction where one wire crosses another and at least one connector species connecting the pair of crossed wires in the junction. The connector species comprises a bi-stable molecule. A plurality of switches is configurable as an AND gate and a plurality of switches is configurable as an OR gate.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: May 24, 2011
    Assignees: Hewlett-Packard Company, The Regents of the University of California
    Inventors: Philip J. Kuekes, James R. Heath
  • Patent number: 7947485
    Abstract: Devices and methods for detecting the constituent parts of biological polymers are disclosed. A molecular analysis device comprises a molecule sensor and a molecule guide. The molecule sensor comprises a single electron transistor including a first terminal, a second terminal, and a nanogap or at least one quantum dot positioned between the first terminal and the second terminal. A nitrogenous material disposed on the at least one quantum dot is configured for an interaction with an identifiable configuration of a molecule. The molecule sensor develops an electronic effect responsive to the interaction. The molecule guide is configured for guiding at least a portion of the molecule substantially near the molecule sensor to enable the interaction.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: May 24, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Wei Wu, Zhiyong Li, Shih-Yuan Wang, Philip J. Kuekes
  • Patent number: 7924413
    Abstract: Embodiments of the present invention are related to nanowire-based devices that can be configured and operated as modulators, chemical sensors, and light-detection devices. In one aspect, a nanowire-based device includes a reflective member, a resonant cavity surrounded by at least a portion of the reflective member, and at least one nanowire disposed within the resonant cavity. The nanowire includes at least one active segment selectively disposed along the length of the nanowire to substantially coincide with at least one antinode of light resonating within the cavity. The active segment can be configured to interact with the light resonating within the cavity.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: April 12, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: R. Stanley Williams, Shih-Yuan Wang, Philip J. Kuekes, Theodore I. Kamins, Duncan Stewart, Alexandre M. Bratkovski, Jason Blackstock, Zhiyong Li
  • Patent number: 7922919
    Abstract: Various embodiments of the present invention are directed to crossbar array designs that interfaces wires to address wires, despite misalignments between electrical components and wires. In one embodiment, a nanoscale device may be composed of a first layer of two or more wires and a second layer of two or more address wires that overlays the first layer. The nanoscale device may also include an intermediate layer positioned between the first layer and the second layer. Two or more redundant electrical component patterns may be fabricated within the intermediate layer so that one or more of the electrical component patterns is aligned with the first and second layers.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: April 12, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Wei Wu, Philip J. Kuekes, R. Stanley Williams
  • Patent number: 7910915
    Abstract: A radiation-emitting device includes a nanowire that is structurally and electrically coupled to a first electrode and a second electrode. The nanowire includes a double-heterostructure semiconductor device configured to emit electromagnetic radiation when a voltage is applied between the electrodes. A device includes a nanowire having an active longitudinal segment selectively disposed at a predetermined location within a resonant cavity that is configured to resonate at least one wavelength of electromagnetic radiation emitted by the segment within a range extending from about 300 nanometers to about 2,000 nanometers. Active nanoparticles are precisely positioned in resonant cavities by growing segments of nanowires at known growth rates for selected amounts of time.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: March 22, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Theodore I Kamins, Philip J Kuekes, Stanley Williams
  • Publication number: 20110057683
    Abstract: One embodiment of the present invention is a method for constructing defect-and-failure-tolerant demultiplexers. This method is applicable to nanoscale, microscale, or larger-scale demultiplexer circuits. Demultiplexer circuits can be viewed as a set of AND gates, each including a reversibly switchable interconnection between a number of address lines, or address-line-derived signal lines, and an output signal line. Each reversibly switchable interconnection includes one or more reversibly switchable elements. In certain demultiplexer embodiments, NMOS and/or PMOS transistors are employed as reversibly switchable elements. In the method that represents one embodiment of the present invention, two or more serially connected transistors are employed in each reversibly switchable interconnection, so that short defects in up to one less than the number of serially interconnected transistors does not lead to failure of the reversibly switchable interconnection.
    Type: Application
    Filed: November 16, 2010
    Publication date: March 10, 2011
    Inventors: Warren Robinett, Philip J. Kuekes, R. Stanley Williams
  • Patent number: 7899091
    Abstract: Embodiments of the present invention include defect-tolerant demultiplexer crossbars that employ, or that can be modeled by demultiplexer crossbars that employ, threshold logic “TL” elements. The threshold-logic elements provide for tolerance for signal variation on internal signals lines of a defect-tolerant demultiplexer crossbar, and thus tolerance for defects which produce internal signal variation.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: March 1, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ron M. Roth, Joseph Warren Robinett, Philip J. Kuekes, R. Stanley Williams
  • Publication number: 20110024714
    Abstract: A nanoscale three-terminal switching device has a bottom electrode, a top electrode, and a side electrode, each of which may be a nanowire. The top electrode extends at an angle with respect to the bottom electrode and has an end section going over and overlapping the bottom electrode. An active region is disposed between the top electrode and bottom electrode and contains a switching material. The side electrode is disposed opposite from the top electrode and in electrical contact with the active region. A self-aligned fabrication process may be used to automatically align the formation of the top and side electrodes with respect to the bottom electrode.
    Type: Application
    Filed: July 30, 2009
    Publication date: February 3, 2011
    Inventors: Wei Wu, Qiangfei Xia, Philip J. Kuekes, R. Stanley Williams