Patents by Inventor Philip Pan
Philip Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11959868Abstract: Embodiments disclosed herein include gas concentration sensors, and methods of using such gas concentration sensors. In an embodiment, a gas concentration sensor comprises a first electrode. In an embodiment the first electrode comprises first fingers. In an embodiment, the gas concentration sensor further comprises a second electrode. In an embodiment, the second electrode comprises second fingers that are interdigitated with the first fingers.Type: GrantFiled: February 3, 2021Date of Patent: April 16, 2024Assignee: Applied Materials, Inc.Inventors: Xiaopu Li, Kallol Bera, Yaoling Pan, Kelvin Chan, Amir Bayati, Philip Allan Kraus, Kenric T. Choi, William John Durand
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Patent number: 9548103Abstract: An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM. A method for selectively configuring a memory array between a CRAM mode and SRAM mode are provided.Type: GrantFiled: July 23, 2015Date of Patent: January 17, 2017Assignee: Altera CorporationInventors: Philip Pan, Andy L. Lee, Lu Zhou, Aniket Kadkol
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Patent number: 9166589Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.Type: GrantFiled: October 2, 2013Date of Patent: October 20, 2015Assignee: Altera CorporationInventors: Philip Pan, Chiakang Sung, Joseph Huang, Yan Chong, Bonnie I. Wang
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Patent number: 9123437Abstract: An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM. A method for selectively configuring a memory array between a CRAM mode and SRAM mode are provided.Type: GrantFiled: December 31, 2013Date of Patent: September 1, 2015Assignee: Altera CorporationInventors: Philip Pan, Andy L. Lee, Lu Zhou, Aniket Kadkol
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Patent number: 8819607Abstract: A method and circuit with minimized clock skews in an IC.Type: GrantFiled: May 31, 2013Date of Patent: August 26, 2014Assignee: Altera CorporationInventors: Philip Pan, Yen-Fu Lin, Ling Yu, Prosenjit Mal
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Publication number: 20140049287Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.Type: ApplicationFiled: October 2, 2013Publication date: February 20, 2014Applicant: ALTERA CORPORATIONInventors: Philip Pan, Chiakang Sung, Joseph Huang, Yan Chong, Bonnie I. Wang
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Patent number: 8644100Abstract: An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM. A method for selectively configuring a memory array between a CRAM mode and SRAM mode are provided.Type: GrantFiled: October 20, 2011Date of Patent: February 4, 2014Assignee: Altera CorporationInventors: Philip Pan, Andy L. Lee, Lu Zhou, Aniket Kadkol
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Patent number: 8593195Abstract: A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.Type: GrantFiled: September 13, 2012Date of Patent: November 26, 2013Assignee: Altera CorporationInventors: Joseph Huang, Chiakang Sung, Philip Pan, Yan Chong, Andy L. Lee, Brian D. Johnson
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Patent number: 8575957Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.Type: GrantFiled: December 13, 2011Date of Patent: November 5, 2013Assignee: Altera CorporationInventors: Philip Pan, Chiakang Sung, Joseph Huang, Yan Chong, Bonnie I. Wang
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Patent number: 8487665Abstract: Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.Type: GrantFiled: May 31, 2011Date of Patent: July 16, 2013Assignee: Altera CorporationInventors: Bonnie I. Wang, Chiakang Sung, Joseph Huang, Khai Nguyen, Philip Pan
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Patent number: 8305121Abstract: A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.Type: GrantFiled: June 24, 2011Date of Patent: November 6, 2012Assignee: Altera CorporationInventors: Joseph Huang, Chiakang Sung, Philip Pan, Yan Chong, Andy L. Lee, Brian D. Johnson
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Publication number: 20120146700Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.Type: ApplicationFiled: December 13, 2011Publication date: June 14, 2012Applicant: ALTERA CORPORATIONInventors: Philip Pan, Chiakang Sung, Joseph Huang, Yan Chong, Bonnie I. Wang
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Publication number: 20120039142Abstract: An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM. A method for selectively configuring a memory array between a CRAM mode and SRAM mode are provided.Type: ApplicationFiled: October 20, 2011Publication date: February 16, 2012Inventors: Philip Pan, Andy L. Lee, Lu Zhou, Aniket Kadkol
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Patent number: 8098082Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.Type: GrantFiled: November 24, 2010Date of Patent: January 17, 2012Assignee: Altera CorporationInventors: Philip Pan, Chiakang Sung, Joseph Huang, Yan Chong, Bonnie I. Wang
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Patent number: 8064280Abstract: An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM. A method for selectively configuring a memory array between a CRAM mode and SRAM mode are provided.Type: GrantFiled: June 10, 2008Date of Patent: November 22, 2011Assignee: Altera CorporationInventors: Philip Pan, Andy L. Lee, Lu Zhou, Aniket Kadkol
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Publication number: 20110227606Abstract: Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.Type: ApplicationFiled: May 31, 2011Publication date: September 22, 2011Applicant: ALTERA CORPORATIONInventors: Bonnie I. Wang, Chiakang Sung, Joseph Huang, Khai Nguyen, Philip Pan
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Patent number: 7969215Abstract: A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.Type: GrantFiled: May 18, 2009Date of Patent: June 28, 2011Assignee: Altera CorporationInventors: Joseph Huang, Chiakang Sung, Philip Pan, Yan Chong, Andy L. Lee, Brian D. Johnson
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Patent number: 7859304Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.Type: GrantFiled: December 6, 2008Date of Patent: December 28, 2010Assignee: Altera CorporationInventors: Philip Pan, Chiakang Sung, Joseph Huang, Yan Chong, Bonnie I. Wang
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Patent number: 7812633Abstract: A programmable logic device having a Logic Element with an N-stage Look Up Table (LUT), dedicated hardware for performing a non-LUT logic function, and an over-ride element configured to selectively force a muxing stage within the N-stage LUT to select either one or more LUT configuration bit inputs or the output of the non-LUT logic function as the output of the LUT. In various embodiments, the non-LUT functions can include addition, subtraction, multiplication, division, digital signal processing, memory storage, etc.Type: GrantFiled: October 20, 2006Date of Patent: October 12, 2010Assignee: Altera CorporationInventors: Andy L. Lee, David Lewis, Philip Pan, James G. Schleicher, II
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Patent number: 7768430Abstract: An integrated circuit (IC) having selectable memory elements is provided. The IC includes a logic array block (LAB) disposed within the IC. A plurality of logic elements, having look-up tables functioning as the selectable memory elements is included in the LAB. Within a logic element, a data path that shares multiplexers and drivers when the look-up tables of the logic elements are operated as one of a memory element or a combinational logic device is provided. In addition, a write address decoder is interconnected with the plurality of logic elements through a write bus.Type: GrantFiled: May 20, 2008Date of Patent: August 3, 2010Assignee: Altera CorporationInventors: Philip Pan, Andy L. Lee