Abstract: Methods and apparatus for delaying a clock signal for a multiple-data-rate interface. An apparatus provides an integrated circuit including a frequency divider configured to receive a first clock signal and a first variable-delay block configured to receive an output from the frequency divider. Also included is a phase detector configured to receive the first clock signal and an output from the first variable-delay block, and an up/down counter configured to receive an output from the phase detector. A second variable-delay block is configured to receive a second clock signal and a plurality of flip-flops are configured to receive an output from the second variable-delay block. The first variable-delay block and the second variable-delay block are configured to receive an output from the up/down counter.

Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

Abstract: A supply voltage detection circuit determines when the voltage for any one of the power supply signals received by an integrated circuit device is below its steady state level, as may occur during a hot socket condition when the device is inserted in or removed from a powered-on system. A first detection circuit determines when the first supply voltage level is below its steady state level, and a second detection circuit determines when the second supply voltage level is below its steady state level. A logic circuit provides a detected condition signal that disables current flow through an input/output terminal associated with the supply voltage detection circuit. The circuit is able to rapidly detect hot socket conditions for a wide range of power supply signal levels, including low supply signal levels, while limiting leakage current effects.

Abstract: Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

Abstract: Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

Abstract: Phase comparators for use in loop circuits (i.e., DLL circuits and PLL circuits) are provided. The phase comparators include a phase detector for comparing a reference clock signal and a feedback signal derived from the loop circuit generated internal clock signal. The phase comparators also include a low-pass noise filter for filtering out erroneously detected phase differences between the reference clock signal and the feedback signal by requiring a certain net number of leading or lagging detections before the compensation circuitry of the loop circuit (i.e., the controlled delay line in a DLL circuit or the controlled oscillator in a PLL circuit) is adjusted. The number of net measurements required before these adjustments take place depends on a programmable bandwidth signal provided to the phase comparator.

Abstract: A memory cell of a programmable device includes a memory partitioning circuit to partition a multiple port memory device into one or more single port memory partitions. The memory partitioning circuit prevents cross addressing by setting the value of one or more address lines of each memory port to a fixed value. The memory partitioning circuit holds address lines at their required values during the programmable device's normal, clear, and reset modes of operation. The behavior of the memory partitioning circuit is set by a portion of a device configuration used to configure the programmable device. The memory partitioning circuit is connected between a memory cell's address register and row or column decoders used to access the multiple port memory device. The memory partitioning circuit can also perform bit-wise inversion operations on portions of the memory addresses.

Abstract: Phase comparators for use in loop circuits (i.e., DLL circuits and PLL circuits) are provided. The phase comparators include a phase detector for comparing a reference clock signal and a feedback signal derived from the loop circuit generated internal clock signal. The phase comparators also include a low-pass noise filter for filtering out erroneously detected phase differences between the reference clock signal and the feedback signal by requiring a certain net number of leading or lagging detections before the compensation circuitry of the loop circuit (i.e., the controlled delay line in a DLL circuit or the controlled oscillator in a PLL circuit) is adjusted. The number of net measurements required before these adjustments take place depends on a programmable bandwidth signal provided to the phase comparator.

Abstract: A supply voltage detection circuit determines when the voltage for any one of the power supply signals received by an integrated circuit device is below its steady state level, as may occur during a hot socket condition when the device is inserted in or removed from a powered-on system. A first detection circuit determines when the first supply voltage level is below its steady state level, and a second detection circuit determines when the second supply voltage level is below its steady state level. A logic circuit provides a detected condition signal that disables current flow through an input/output terminal associated with the supply voltage detection circuit. The circuit is able to rapidly detect hot socket conditions for a wide range of power supply signal levels, including low supply signal levels, while limiting leakage current effects.

Abstract: Techniques are provided for recycling addresses in memory blocks. Address signals in memory blocks are stored temporarily in a set of parallel coupled address registers. The address registers transfer the address signals to an address decoder block, which decodes the address signals. The address decoder block transfers the decoded addresses to a memory array. A stall state occurs when the cache memory block needs a new set of data to replace the old set of data. Address signals are stored in the address registers during the stall state by coupling each register's output to its data input using a series of multiplexers. The multiplexers are controlled by an address stall signal that indicates the onset and the end of a stall state. After the end of a stall state, the address registers store the next address signal received at the memory block.

Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

Abstract: A switch circuit selectively provides a reference voltage, needed in some I/O standards, to a logic device. The circuit receives a dedicated power supply that is different from the device's I/O supply. It may also include a level shifting circuit for converting a master control signal having a logic level determined by a first supply to a first control signal having a logic level determined by the dedicated supply. The switch circuit also includes a transmission switch that passes the reference voltage to an output in response to at least the first control signal. The transmission switch may be a CMOS transmission gate with at least one NMOS transistor controlled by the first control signal in parallel with at least one PMOS transistor controlled by a second control signal, complementary to the first. The second control signal may be generated by another level shifting circuit and have a logic level determined by the I/O supply.

Abstract: Techniques for preloading data into memory blocks on a programmable circuit are provided. Memory blocks on the a programmable circuit each have dedicated circuitry that loads data into the memory block. The dedicated circuit also generates memory addresses used to load the data into the memory block. The dedicated circuitry associated with each memory block reduces demand on the routing resources. A user can preload data into the memory blocks prior to user mode. A user can also prevent data from being preloaded into one or more of the memory blocks prior to user mode. By allowing the user to program some or all of the memory blocks prior to user mode, the time needed to a program the memory blocks prior to user mode can be substantially reduced.

Abstract: Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

Abstract: A supply voltage detection circuit determines when the voltage for any one of the power supply signals received by an integrated circuit device is below its steady state level, as may occur during a hot socket condition when the device is inserted in or removed from a powered-on system. A first detection circuit determines when the first supply voltage level is below its steady state level, and a second detection circuit determines when the second supply voltage level is below its steady state level. A logic circuit provides a detected condition signal that disables current flow through an input/output terminal associated with the supply voltage detection circuit. The circuit is able to rapidly detect hot socket conditions for a wide range of power supply signal levels, including low supply signal levels, while limiting leakage current effects.

Abstract: A Schmitt trigger circuit has an adjustable hysteresis characteristic by providing a plurality of feedback circuits that differently affect at least one, and preferably both, of the circuit's upper trip point level and lower trip point level. The upper trip point level can be adjusted by selecting a desired feedback circuit from a first set of feedback circuits, and/or the lower trip point level can be adjusted by selecting a desired feedback circuit from a second set of feedback circuits. Feedback circuit selection is achieved by one or more control signals that may be programmable. The hysteresis characteristic can be adjusted to meet desired noise margin, delay, and input recognition criteria at different VCC levels. The Schmitt trigger circuit may be a CMOS Schmitt trigger with two input stage NMOS, two input stage PMOS transistors, a first set of NMOS feedback circuits, and a second set of PMOS feedback circuits.

Abstract: Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

Abstract: An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.

Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

Abstract: Techniques and circuitry are used to more rapidly configuring programmable integrated circuits. Configuration data is input into a programmable integrated circuit in parallel via parallel inputs (705), and this data is also handled internally in parallel. The configuration data will be stored in a data register (722). This data register includes two or more serial register chains, each chain being made up of a serial chain of registers. The configuration data is input into the two of more chains of the data registers in parallel. Circuitry is also provided to handle redundancy.