Abstract: An isolation region (14) is formed between an edge termination region (2) having deep trenches (20,34) and the central region (4). The isolation region includes gate fingers (18) extending from the edge gate trench regions (28) to the gate trenches (6) in the central region (4) to electrically connect the edge gate trench regions to the gate trenches (6) in the central region. The isolation region also includes isolation fingers (22,24) extending from the edge termination region (2) towards the central region (4) and gate between the gate fingers (18) for reducing the breakdown voltage with a RESURF effect.

Abstract: A Trench gate MOS field-effect transistor having a narrow, lightly doped, region extending from a channel accommodating region (3) of same conductivity type immediately adjacent the trench sidewall. The narrow region may be self-aligned to the top of a lower polysilicon shield region in the trench or may extend the complete depth of the trench. The narrow region advantageously relaxes the manufacturing tolerances, which otherwise require close alignment of the upper polysilicon trench gate to the body-drain junction.

Abstract: A method of manufacturing a semiconductor device is presented. The device has: a gate terminal formed from polysilicon and covered by an insulation layer; and a plug extending through an insulation layer to provide an electrical connection to the gate trench. A metal layer is deposited to cover at least a portion of the insulation layer. The metal layer is then etched to remove the metal layer from above the plug.

Abstract: An isolation region (14) is formed between an edge termination region (2) having deep trenches (20,34) and the central region (4). The isolation region includes gate fingers (18) extending from the edge gate trench regions (28) to the gate trenches (6) in the central region (4) to electrically connect the edge gate trench regions to the gate trenches (6) in the central region. The isolation region also includes isolation fingers (22,24) extending from the edge termination region (2) towards the central region (4) and gate between the gate fingers (18) for reducing the breakdown voltage with a RESURF effect.

Abstract: A Trench gate MOS field-effect transistor having a narrow, lightly doped, region extending from a channel accommodating region (3) of same conductivity type immediately adjacent the trench sidewall. The narrow region may be self-aligned to the top of a lower polysilicon shield region in the trench or may extend the complete depth of the trench. The narrow region advantageously relaxes the manufacturing tolerances, which otherwise require close alignment of the upper polysilicon trench gate to the body-drain junction.

Abstract: A dc-to-dc converter has two field effect transistors connected in series between an input terminal and a ground terminal. Adjustment of the dead time when both transistors are off is carried out by providing Kelvin feedback connections directly across the drain and source of one or both of the transistors, so bypassing signal line resistance and inductances.

Abstract: Consistent with an example embodiment a trench-gate semiconductor device, for example a MOSFET or IGBT, having a field plate provided below the trenched gate is manufactured using a process with improved reproducibility. The process includes the steps of etching a first grove into the semiconductor body for receiving the gate, and etching a second groove into the top major surface of the semiconductor body, the second groove extending from the first groove and being narrower than the first groove. The invention enables better control of the vertical extent of the gate below the top major surface of the semiconductor body.

Abstract: A driver circuit includes monitoring circuitry (32, 34, 36) for monitoring the states of high and low side switches (6, 8). The driver circuit has an adjustable delay for turning on the transistors (6, 8). The delay is decreased when the monitoring circuit detects that a voltage corresponding to one transistor passes a predetermined voltage V1 before a voltage corresponding to the other transistor passes another predetermined point V2, and vice versa.

Abstract: A multilayer white polymeric film having a core layer with an optical transmission density greater than 2.0, a white polyester outer layer on either side of the core layer and an ink receptive layer on the outer surface of the white polyester layers.

Abstract: A trench-gate semiconductor device, for example a MOSFET or IGBT, includes a semiconductor body (20) having a drain region (4) comprising a drain drift region (4a) and a drain contact region (4b). An insulated field plate (24) is included in the trench (10) between the gate (8) and the drain contact region (4b), wherein the field plate (24) is for connection to a bias potential greater than the gate potential and near to the bulk breakdown voltage of the drain drift region (4a). The field plate (24) causes the potential drop across the drain drift region (4a) to be spread considerably more evenly, particularly at applied voltages greater than the bulk breakdown voltage, thereby substantially increasing the breakdown voltage of the device.

Abstract: A device termination structure, and/or a gate bus-bar structure, and/or other end structure is provided for at least one group of cells in a cellular trench-gate semiconductor device, for example a power MOSFET. In this end structure, a conductive layer (11c), for example of polysilicon gate material, extends on an intermediate insulating layer (55) over a higher-doped (P+) end region (150) of the channel-accommodating region (15). This insulating layer (55) comprises an area (51e) of a trench-etch mask (51), preferably comprising silicon nitride, that is of greater thickness than the gate dielectric layer (17). A window (51a) extends through the trench-etch mask (51) at a location where an end trench (20e) extends into the P+ region (150). The end trench (20e) is an extension of the insulated gate trench (20) into the P+ region (150) and accommodates an extension (11e) of the trench-gate (11). The conductive layer (11c) is connected to the trench-gate extension (11e) via the window (51e).

Abstract: A power switching circuit has high and low side switches (6, 8). The load-side FET (8) has a main body part (30) and a sense FET part (32). The current sensing circuit (32) measured the low side current. A capacitance (56) couples the switch node (10) to a current signal node (52) to provide a combined signal on current output (58), the combined signal including the low side current and timing information.

Abstract: The trend towards more digital signal processing in mains-powered devices causes an increasing variety of supply voltages at ever decreasing levels and at higher currents. At present, the secondary side architecture provides a separate ac-dc conversion and dc-dc down-conversion stages in order to obtain stabilized voltages at those low levels. According to the present invention, a controlling synchronous rectifier is provided, comprising a power MOSFET and a control unit which allow to integrate both stages. In particular, according to the present invention, the output voltage of the synchronous rectifier is controlled by controlling the channel switching of the MOSFET. Advantageously, this provides for a very simple and efficient rectification and voltage control.

Abstract: A dc-to-dc converter has two field effect transistors (35, 36) connected in series between an input terminal (37) and a ground terminal (38). Adjustment of the dead time when both transistors (35, 36) are off is carried out by providing Kelvin feedback connections (71, 72, 67, 68) directly across the drain (39, 44) and source (43, 40) of one or both of the transistors (35, 36), so bypassing signal line resistance and inductances.

Abstract: A power switching circuit has high and low side switches (6, 8). The load-side FET (8) has a main body part (30) and a sense FET part (32). The current sensing circuit (32) measured the low side current. A capacitance (56) couples the switch node (10) to a current signal node (52) to provide a combined signal on current output (58), the combined signal including the low side current and timing information.

Abstract: A driver circuit includes monitoring circuitry (32, 34, 36) for monitoring the states of high and low side switches (6, 8). The driver circuit has an adjustable delay for turning on the transistors (6, 8). The delay is decreased when the monitoring circuit detects that a voltage corresponding to one transistor passes a predetermined voltage V1 before a voltage corresponding to the other transistor passes another predetermined point V2, and vice versa.

Abstract: A trench-gate semiconductor device, for example a MOSFET or IGBT, having a field plate (24) provided below the trenched gate (8) is manufactured using a process with improved reproducibility. The process includes the steps of etching a first grove (28a) into the semiconductor body (20) for receiving the gate (8), and etching a second groove (28b) into the top major surface (20a) of the semiconductor body (20), the second groove (28b) extending from the bottom of the first groove (28a) and being narrower than the first grove. The invention enables better control of the vertical extent of the gate below the top major surface (20a) of the semiconductor body.

Abstract: A trench-gate semiconductor device, for example a MOSFET or IGBT, includes a semiconductor body (20) having a drain region (4) comprising a drain drift region (4a) and a drain contact region (4b). An insulated field plate (24) is included in the trench (10) between the gate (8) and the drain contact region (4b), wherein the field plate (24) is for connection to a bias potential greater than the gate potential and near to the bulk breakdown voltage of the drain drift region (4a). The field plate (24) causes the potential drop across the drain drift region (4a) to be spread considerably more evenly, particularly at applied voltages greater than the bulk breakdown voltage, thereby substantially increasing the breakdown voltage of the device.

Abstract: In a multi-chip module semiconductor device (1), at least one first semiconductor die (20) is mounted on the base portion (11) of a lead-frame (10). A flip chip IC die (30) is mounted by first bump electrodes (31) to electrode contacts (G, S?) on the at least one first die (20) and by second bump electrodes (32) to terminal pins (14) of the lead frame. The integrated circuit of the flip chip (30) does not require any lead-frame base-portion area for mounting, and low impedance circuit connections are provided by the bump electrodes (31, 32). The first die (20) may be a MOSFET power switching transistor, with a gate driver circuit in the flip chip (30). The circuit impedance for the switching transistor may be further reduced by having distributed parallel gate connections (G), which may alternate with distributed parallel source connections (S?), and furthermore by having distributed and alternating power supply connections (VCC, GND).

Abstract: A device termination structure, and/or a gate bus-bar structure, and/or other end structure is provided for at least one group of cells in a cellular trench-gate semiconductor device, for example a power MOSFET. In this end structure, a conductive layer (11c), for example of polysilicon gate material, extends on an intermediate insulating layer (55) over a higher-doped (P+) end region (150) of the channel-accommodating region (15). This insulating layer (55) comprises an area (51e) of a trench-etch mask (51), preferably comprising silicon nitride, that is of greater thickness than the gate dielectric layer (17). A window (51a) extends through the trench-etch mask (51) at a location where an end trench (20e) extends into the P+ region (150). The end trench (20e) is an extension of the insulated gate trench (20) into the P+ region (150) and accommodates an extension (11e) of the trench-gate (11). The conductive layer (11c) is connected to the trench-gate extension (11e) via the window (51e).