Patents by Inventor Phillip J. Restle

Phillip J. Restle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200019224
    Abstract: A voltage droop mitigation system, that includes a first processor core that executes computer executable components stored in a memory. A time-based sensor component generates digital data representing voltage values associated with a power supply. A filtering component digitally conditions the generated digital data, and an analysis component analyzes the conditioned data and determines slope of the power supply voltage and employs counters to determine rate of data change over time; and if the slope is negative and exceeds a first pre-determined value for a pre-determined time period. The system implements one or more voltage droop-reduction techniques at the first processor core; and the first processor core transmits at least one of the following types of information: its voltage value, slope information or decision to apply droop reduction to one or more other cores.
    Type: Application
    Filed: August 14, 2019
    Publication date: January 16, 2020
    Inventors: Pierce I-Jen Chuang, Phillip J. Restle, Christos Vezyrtzis, Divya Pathak
  • Patent number: 10437311
    Abstract: A voltage droop mitigation system, that includes a first processor core that executes computer executable components stored in a memory. A time-based sensor component generates digital data representing voltage values associated with a power supply. A filtering component digitally conditions the generated digital data, and an analysis component analyzes the conditioned data and determines slope of the power supply voltage and employs counters to determine rate of data change over time; and if the slope is negative and exceeds a first pre-determined value for a pre-determined time period. The system implements one or more voltage droop-reduction techniques at the first processor core; and the first processor core transmits at least one of the following types of information: its voltage value, slope information or decision to apply droop reduction to one or more other cores.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: October 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Pierce I. Chuang, Divya Pathak, Phillip J. Restle, Christos Vezyrtzis
  • Patent number: 10261561
    Abstract: A voltage droop mitigation system, that includes a first processor core that executes computer executable components stored in a memory. A time-based sensor component generates digital data representing voltage values associated with a power supply. A filtering component digitally conditions the generated digital data, and an analysis component analyzes the conditioned data and determines slope of the power supply voltage and employs counters to determine rate of data change over time; and if the slope is negative and exceeds a first pre-determined value for a pre-determined time period. The system implements one or more voltage droop-reduction techniques at the first processor core; and the first processor core transmits at least one of the following types of information: its voltage value, slope information or decision to apply droop reduction to one or more other cores.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: April 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pierce I. Chuang, Phillip J. Restle, Christos Vezyrtzis
  • Patent number: 10145892
    Abstract: A method for increasing a resolution of an on-chip measurement circuit is provided. The method includes propagating a first signal through the on-chip measurement circuit to generate a first output. The method also includes propagating a second signal through the on-chip measurement circuit to generate a second output. The second signal includes a delay. The method also includes reconciling the first output and the second output to determine the resolution of the on-chip measurement circuit. The resolution of the on-chip measurement circuit increases in correspondence with a fineness of a step of the delay.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: December 4, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, COMPUTER TASK GROUP, INC.
    Inventors: Robert L. Franch, Phillip J. Restle, Thomas Strach, Christos Vezyrtzis, Scott F. Warnock
  • Patent number: 10141915
    Abstract: A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: November 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas J. Bucelot, Phillip J. Restle, David Wen-Hao Shan
  • Publication number: 20180067532
    Abstract: A voltage droop mitigation system, that includes a first processor core that executes computer executable components stored in a memory. A time-based sensor component generates digital data representing voltage values associated with a power supply. A filtering component digitally conditions the generated digital data, and an analysis component analyzes the conditioned data and determines slope of the power supply voltage and employs counters to determine rate of data change over time; and if the slope is negative and exceeds a first pre-determined value for a pre-determined time period. The system implements one or more voltage droop-reduction techniques at the first processor core; and the first processor core transmits at least one of the following types of information: its voltage value, slope information or decision to apply droop reduction to one or more other cores.
    Type: Application
    Filed: September 6, 2016
    Publication date: March 8, 2018
    Inventors: PIERCE I. CHUANG, DIVYA PATHAK, PHILLIP J. RESTLE, CHRISTOS VEZYRTZIS
  • Publication number: 20180067541
    Abstract: A voltage droop mitigation system, that includes a first processor core that executes computer executable components stored in a memory. A time-based sensor component generates digital data representing voltage values associated with a power supply. A filtering component digitally conditions the generated digital data, and an analysis component analyzes the conditioned data and determines slope of the power supply voltage and employs counters to determine rate of data change over time; and if the slope is negative and exceeds a first pre-determined value for a pre-determined time period. The system implements one or more voltage droop-reduction techniques at the first processor core; and the first processor core transmits at least one of the following types of information: its voltage value, slope information or decision to apply droop reduction to one or more other cores.
    Type: Application
    Filed: September 6, 2016
    Publication date: March 8, 2018
    Inventors: PIERCE I. CHUANG, PHILLIP J. RESTLE, CHRISTOS VEZYRTZIS
  • Publication number: 20180052200
    Abstract: A method for increasing a resolution of an on-chip measurement circuit is provided. The method includes propagating a first signal through the on-chip measurement circuit to generate a first output. The method also includes propagating a second signal through the on-chip measurement circuit to generate a second output. The second signal includes a delay. The method also includes reconciling the first output and the second output to determine the resolution of the on-chip measurement circuit. The resolution of the on-chip measurement circuit increases in correspondence with a fineness of a step of the delay.
    Type: Application
    Filed: August 22, 2016
    Publication date: February 22, 2018
    Inventors: ROBERT L. FRANCH, PHILLIP J. RESTLE, THOMAS STRACH, CHRISTOS VEZYRTZIS, SCOTT F. WARNOCK
  • Patent number: 9800232
    Abstract: A method for providing a stitchable clock mesh, a dual operation mode system, and a method for providing a master clock stratum are, in turn, provided for a 3D chip stack having two or more strata. The method for providing a stitchable clock mesh includes providing, by at least one clock mesh disposed on each stratum and having multiple sectors, a global clock signal to various chip locations. The method further includes collecting, by mesh data sensors on each stratum, mesh data for the at least one mesh. The mesh data includes measured functional data and measured performance data for a current system configuration. The method also includes selectively performing, by joining circuitry, a segmentation operation or a joining operation on the least one mesh or one or more portions thereof responsive to the mesh data and the current system configuration selectable from a plurality of system target configurations.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: October 24, 2017
  • Publication number: 20170207772
    Abstract: A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.
    Type: Application
    Filed: April 5, 2017
    Publication date: July 20, 2017
    Inventors: Thomas J. Bucelot, Phillip J. Restle, David Wen-Hao Shan
  • Patent number: 9705479
    Abstract: A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: July 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas J. Bucelot, Phillip J. Restle, David Wen-Hao Shan
  • Patent number: 9634654
    Abstract: A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: April 25, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas J. Bucelot, Phillip J. Restle, David Wen-Hao Shan
  • Patent number: 9618966
    Abstract: A pulse-drive resonant clock with on-the fly mode changing provides robust operation in a resonant clock distribution network, in particular for processor circuits having a dynamically-varied operating frequency. The clock drivers for the resonant clock distribution network include a pulse width control circuit having selectable operating modes corresponding to multiple clocking modes of the resonant clock distribution network. The pulse width control circuit includes a delay line that has a selectable delay length to provide pulse enable signals that control the pulse widths of the clock drivers in a sector of the resonant clock distribution network. The delay line responds to a mode control signal so that at least one pulse width of the output is changed from a first pulse width to a second pulse width without generating half-cycles with a pulse width narrower than the first or second pulse width.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: April 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas J. Bucelot, Robert L. Franch, Phillip J. Restle, David Wen-Hao Shan, Christos Vezyrtzis
  • Patent number: 9612614
    Abstract: A pulse-drive resonant clock with on-the fly mode changing provides robust operation in a resonant clock distribution network, in particular for processor circuits having a dynamically-varied operating frequency. The clock drivers for the resonant clock distribution network include a pulse width control circuit having selectable operating modes corresponding to multiple clocking modes of the resonant clock distribution network. The pulse width control circuit includes a delay line that has a selectable delay length to provide pulse enable signals that control the pulse widths of the clock drivers in a sector of the resonant clock distribution network. The delay line responds to a mode control signal so that at least one pulse width of the output is changed from a first pulse width to a second pulse width without generating half-cycles with a pulse width narrower than the first or second pulse width.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: April 4, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas J. Bucelot, Robert L. Franch, Phillip J. Restle, David Wen-Hao Shan, Christos Vezyrtzis
  • Patent number: 9612612
    Abstract: A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: April 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Thomas J. Bucelot, Alan J. Drake, Robert A. Groves, Jason D. Hibbeler, Yong I. Kim, Liang-Teck Pang, William R. Reohr, Phillip J. Restle, Michael G. R. Thomson
  • Patent number: 9575119
    Abstract: A delay measurement technique using a tapped delay line edge capture circuit that captures tap position of edges within the delay line provides accuracy of measurement to one pico-second and below. A control circuit causes latches to capture an edge of a signal delayed through the delay line at taps of the delay line. The frequency of a clock from which the signal is derived is adjusted and tap outputs are captured by latches and averaged. A first frequency is found at which the average edge position is midway between two adjacent tap positions. A second signal, which may be the reference signal that clocks the latches, is propagated through the delay line and a second frequency is found for which the average edge position lies at the boundary between the two tap positions. The delay is determined from the difference between the periods of the first frequency and the second frequency.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: February 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert L. Franch, Phillip J. Restle, David Wen-Hao Shan
  • Patent number: 9568548
    Abstract: A delay measurement technique using a tapped delay line edge capture circuit that captures tap position of edges within the delay line provides accuracy of measurement to one pico-second and below. A control circuit causes latches to capture an edge of a signal delayed through the delay line at taps of the delay line. The frequency of a clock from which the signal is derived is adjusted and tap outputs are captured by latches and averaged. A first frequency is found at which the average edge position is midway between two adjacent tap positions. A second signal, which may be the reference signal that clocks the latches, is propagated through the delay line and a second frequency is found for which the average edge position lies at the boundary between the two tap positions. The delay is determined from the difference between the periods of the first frequency and the second frequency.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert L. Franch, Phillip J. Restle, David Wen-Hao Shan
  • Patent number: 9571100
    Abstract: A clock driver is provided. The clock driver includes a multi-stage delay cell having an input, a positive pulse driving branch, a negative pulse driving branch, and an output. The input is for receiving an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. The output is connected to the positive pulse driving branch and the negative pulse driving branch. The clock driver further includes a pulse generator having positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: February 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Aditya Bansal, Thomas J. Bucelot, Alan J. Drake, Phillip J. Restle, David W. Shan, Mrigank Sharad
  • Publication number: 20170040981
    Abstract: A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.
    Type: Application
    Filed: August 18, 2015
    Publication date: February 9, 2017
    Inventors: Thomas J. Bucelot, Phillip J. Restle, David Wen-Hao Shan
  • Publication number: 20170040987
    Abstract: A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits.
    Type: Application
    Filed: August 7, 2015
    Publication date: February 9, 2017
    Inventors: Thomas J. Bucelot, Phillip J. Restle, David Wen-Hao Shan