Abstract: An apparatus includes a shaft and an end effector at a distal end of the shaft. The end effector is sized to fit in an anatomical passageway within a subject's cardiovascular system. The end effector includes at least one electrode pair that is configured to contact cardiovascular tissue and thereby pick up electrocardiogram signals. Each electrode pair includes first and second electrodes spaced apart along a longitudinal axis from each other by a gap area located between the electrodes, the gap area having a gap length with respect to the longitudinal axis such that a length of one of the electrodes along the longitudinal axis is equal to or greater than the gap length; and a ratio of an area defined by the gap area to one electrode area is equal to or less than one.

Abstract: A wafer includes a semiconductor substrate, an interconnection network provided with metal layers and at least one ultra-low dielectric constant dielectric layer, at least one contact region and at least one dicing region. A hard mask is formed having a pattern that defines a dicing line. The formation of the hard mask includes a first etching of an opening in the dicing region to expose the semiconductor substrate in the dicing region, a second etching of an opening in the contact region to expose a surface of a metal contact in the contact region, and a chemical treatment for cleaning the uncovered surface of the metal contact. A vertical dielectric layer is deposited to cover edges of the opening defining the dicing line. This layer is deposited before the chemical treatment is performed.

Abstract: In an embodiment a method for manufacturing an image sensor includes forming of a plurality of microlenses at a first resin layer, forming a mask on top of and in contact with the first resin layer, the mask comprising a second resin; and chemical plasma etching the first resin layer through the mask.

Abstract: The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.

Abstract: The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.

Abstract: A cavity is etched in a stack of layers which includes a first layer made of a first material and a second layer made of a second material. To etch the cavity, a first etch mask having a first opening is formed over the stack of layer. The stack of layers is then etched through the first opening to a depth located in the second layer. A second mask having a second opening, the dimensions of which are smaller, in top view, than the first opening, is formed over the stack of layer. The second opening is located, in top view, opposite the area etched through the first opening. The second layer is then etched through the second opening to reach the first layer. The etch method used is configured to etch the second material selectively over the first material.

Abstract: The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.

Abstract: A cavity is etched in a stack of layers which includes a first layer made of a first material and a second layer made of a second material. To etch the cavity, a first etch mask having a first opening is formed over the stack of layer. The stack of layers is then etched through the first opening to a depth located in the second layer. A second mask having a second opening, the dimensions of which are smaller, in top view, than the first opening, is formed over the stack of layer. The second opening is located, in top view, opposite the area etched through the first opening. The second layer is then etched through the second opening to reach the first layer. The etch method used is configured to etch the second material selectively over the first material.

Abstract: An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.

Abstract: A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal lines run on the upper surface of the interposer and are arranged between conductive elements of connection to the chip. An end of each first metal line is arranged to extend beyond a projection of the chip on the interposer. A thermally-conductive via connects the end of the first metal line to a heat sink supported at an upper surface of the device.

Abstract: An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.

Abstract: An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.

Abstract: A method for manufacturing a wafer on which are formed resonators, each resonator including, above a semiconductor substrate, a stack of layers including, in the following order from the substrate surface: a Bragg mirror; a compensation layer made of a material having a temperature coefficient of the acoustic velocity of a sign opposite to that of all the other stack layers; and a piezoelectric resonator, the method including the successive steps of: a) depositing the compensation layer; and b) decreasing thickness inequalities of the compensation layer due to the deposition method, so that this layer has a same thickness to within better than 2%, and preferably to within better than 1%, at the level of each resonator.

Abstract: A three-dimensional integrated structure includes a first and a second element each having an interconnection part formed by metallization levels encased in an insulating region. The first and second elements are attached to one another by the respective interconnection parts. The first element includes an electrical connection via passing through a substrate. A thermal cooling system includes at least one cavity having a first part located in the insulating region of the interconnection part of the first element and a second part located in the insulating region of the interconnection part of the second element and at least one through channel extending from a rear face of the first element to open into the at least one cavity.

Abstract: A method and corresponding system are provided for determining a three-dimensional stress field of an object having a flat surface. At least four flat resistors are placed on the flat surface of the object, with at least one of the resistors having a geometry different from that of the others. A variation of resistance of the resistors is measured. The three-dimensional stress field is determined from a system of equations involving the stress field, values of variations of the measured resistive values and sensitivity parameters of the resistors.

Abstract: A three-dimensional integrated structure includes a first and a second element each having an interconnection part formed by metallization levels encased in an insulating region. The first and second elements are attached to one another by the respective interconnection parts. The first element includes an electrical connection via passing through a substrate. A thermal cooling system includes at least one cavity having a first part located in the insulating region of the interconnection part of the first element and a second part located in the insulating region of the interconnection part of the second element and at least one through channel extending from a rear face of the first element to open into the at least one cavity.

Abstract: A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal lines run on the upper surface of the interposer and are arranged between conductive elements of connection to the chip. An end of each first metal line is arranged to extend beyond a projection of the chip on the interposer. A thermally-conductive via connects the end of the first metal line to a heat sink supported at an upper surface of the device.

Abstract: In one embodiment there is disclosed a method for manufacturing an integrated circuit in a semiconductor substrate including through vias and a coplanar line, including the steps of: forming active components and a set of front metallization levels; simultaneously etching from the rear surface of the substrate a through via hole and a trench crossing the substrate through at least 50% of its height; coating with a conductive material the walls and the bottom of the hole and of the trench; and filling the hole and the trench with an insulating filling material; and forming a coplanar line extending on the rear surface of the substrate, in front of the trench and parallel thereto, so that the lateral conductors of the coplanar line are electrically connected to the conductive material coating the walls of the trench.

Abstract: A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal lines run on the upper surface of the interposer and are arranged between conductive elements of connection to the chip. An end of each first metal line is arranged to extend beyond a projection of the chip on the interposer. A thermally-conductive via connects the end of the first metal line to a heat sink supported at an upper surface of the device.

Abstract: In one embodiment there is disclosed a method for manufacturing an integrated circuit in a semiconductor substrate including through vias and a coplanar line, including the steps of: forming active components and a set of front metallization levels; simultaneously etching from the rear surface of the substrate a through via hole and a trench crossing the substrate through at least 50% of its height; coating with a conductive material the walls and the bottom of the hole and of the trench; and filling the hole and the trench with an insulating filling material; and forming a coplanar line extending on the rear surface of the substrate, in front of the trench and parallel thereto, so that the lateral conductors of the coplanar line are electrically connected to the conductive material coating the walls of the trench.