Abstract: In an embodiment a method for manufacturing an image sensor includes forming of a plurality of microlenses at a first resin layer, forming a mask on top of and in contact with the first resin layer, the mask comprising a second resin; and chemical plasma etching the first resin layer through the mask.

Abstract: The present description concerns an image sensor comprising a semiconductor substrate comprising a first surface, a porous layer, made of an electrically-insulating and porous material, on the first surface crossed by openings, a color filter in each opening, a first moisture-proof protection layer covering the porous layer outside of the openings, and a second moisture-proof protection layer covering the covering the first protection layer and the walls of each opening, between the porous layer and the color filter present in the opening.

Abstract: The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.

Abstract: The present description concerns an electronic circuit manufacturing method comprising, in the order, forming an opening in a semiconductor substrate, the semiconductor substrate including a first surface and a second surface opposite to the first surface, the opening positioned between the first surface and the second surface and forming an electrically-conductive pad, the electrically-conductive pad including a first portion positioned over the first surface and a second portion covering the flanks of the opening and delimiting a gap in the opening, and depositing a first layer covering the electrically-conductive pad and filling the gap, the first layer containing a first resin, the first resin being non-photosensitive, and crosslinking the first resin in the first layer, and chemically etching by plasma the first layer to delimit a first block of the first resin in the gap, and depositing a first protection layer on the first block.

Abstract: A method of manufacturing an image sensor comprising the forming of an opening in a substrate, the forming of a conductive pad covering the flanks of the opening and delimiting a gap in the opening, the forming of microlenses in a layer made of a first resin, the layer made of the first resin covering the pad and penetrating into the gap, the forming of a mask made of a second resin on top of and in contact with the layer made of the first resin, the chemical plasma etching of the layer made of the first resin, through the mask, delimiting a block of the first resin in the gap, the deposition of a protective layer on the microlenses and on the block, the removal of the portion of the protective layer covering the block, and the etching of the block.

Abstract: The present description concerns a method of manufacturing an electronic circuit comprising, in the order, the forming on a semiconductor substrate comprising a surface of at least one conductive pad extending over the surface and having sides inclined with respect to the surface, the forming of a first insulating layer on the pad, the deposition of a resin layer and the forming of an opening in the resin layer exposing the entire pad, the plasma etching of the first insulating layer in the opening, which results in the forming of first compounds on the etched edges of the first insulating layer and of second compounds on the pad, the removal of the resin layer, the removal of the first compounds, the removal of the second compounds, and the forming of a second insulating layer on the pad.

Abstract: A wafer includes a semiconductor substrate, an interconnection network provided with metal layers and at least one ultra-low dielectric constant dielectric layer, at least one contact region and at least one dicing region. A hard mask is formed having a pattern that defines a dicing line. The formation of the hard mask includes a first etching of an opening in the dicing region to expose the semiconductor substrate in the dicing region, a second etching of an opening in the contact region to expose a surface of a metal contact in the contact region, and a chemical treatment for cleaning the uncovered surface of the metal contact. A vertical dielectric layer is deposited to cover edges of the opening defining the dicing line. This layer is deposited before the chemical treatment is performed.

Abstract: In an embodiment a method for manufacturing an image sensor includes forming of a plurality of microlenses at a first resin layer, forming a mask on top of and in contact with the first resin layer, the mask comprising a second resin; and chemical plasma etching the first resin layer through the mask.

Abstract: The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.

Abstract: The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.

Abstract: A cavity is etched in a stack of layers which includes a first layer made of a first material and a second layer made of a second material. To etch the cavity, a first etch mask having a first opening is formed over the stack of layer. The stack of layers is then etched through the first opening to a depth located in the second layer. A second mask having a second opening, the dimensions of which are smaller, in top view, than the first opening, is formed over the stack of layer. The second opening is located, in top view, opposite the area etched through the first opening. The second layer is then etched through the second opening to reach the first layer. The etch method used is configured to etch the second material selectively over the first material.

Abstract: The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.

Abstract: A cavity is etched in a stack of layers which includes a first layer made of a first material and a second layer made of a second material. To etch the cavity, a first etch mask having a first opening is formed over the stack of layer. The stack of layers is then etched through the first opening to a depth located in the second layer. A second mask having a second opening, the dimensions of which are smaller, in top view, than the first opening, is formed over the stack of layer. The second opening is located, in top view, opposite the area etched through the first opening. The second layer is then etched through the second opening to reach the first layer. The etch method used is configured to etch the second material selectively over the first material.

Abstract: An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.

Abstract: A device includes a chip assembled on an interposer. An electrically-insulating layer coats an upper surface of the interposer around the chip. First metal lines run on the upper surface of the interposer and are arranged between conductive elements of connection to the chip. An end of each first metal line is arranged to extend beyond a projection of the chip on the interposer. A thermally-conductive via connects the end of the first metal line to a heat sink supported at an upper surface of the device.

Abstract: An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.

Abstract: An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.

Abstract: A three-dimensional integrated structure includes a first and a second element each having an interconnection part formed by metallization levels encased in an insulating region. The first and second elements are attached to one another by the respective interconnection parts. The first element includes an electrical connection via passing through a substrate. A thermal cooling system includes at least one cavity having a first part located in the insulating region of the interconnection part of the first element and a second part located in the insulating region of the interconnection part of the second element and at least one through channel extending from a rear face of the first element to open into the at least one cavity.

Abstract: A method for manufacturing a wafer on which are formed resonators, each resonator including, above a semiconductor substrate, a stack of layers including, in the following order from the substrate surface: a Bragg mirror; a compensation layer made of a material having a temperature coefficient of the acoustic velocity of a sign opposite to that of all the other stack layers; and a piezoelectric resonator, the method including the successive steps of: a) depositing the compensation layer; and b) decreasing thickness inequalities of the compensation layer due to the deposition method, so that this layer has a same thickness to within better than 2%, and preferably to within better than 1%, at the level of each resonator.

Abstract: A method and corresponding system are provided for determining a three-dimensional stress field of an object having a flat surface. At least four flat resistors are placed on the flat surface of the object, with at least one of the resistors having a geometry different from that of the others. A variation of resistance of the resistors is measured. The three-dimensional stress field is determined from a system of equations involving the stress field, values of variations of the measured resistive values and sensitivity parameters of the resistors.