Patents by Inventor Pierre Morin

Pierre Morin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160190304
    Abstract: A modified silicon substrate having a substantially defect-free strain relaxed buffer layer of SiGe is suitable for use as a foundation on which to construct a high performance CMOS FinFET device. The substantially defect-free SiGe strain-relaxed buffer layer can be formed by making cuts in, or segmenting, a strained epitaxial film, causing edges of the film segments to experience an elastic strain relaxation. When the segments are small enough, the overall film is relaxed so that the film is substantially without dislocation defects. Once the substantially defect-free strain-relaxed buffer layer is formed, strained channel layers can be grown epitaxially from the relaxed SRB layer. The strained channel layers are then patterned to create fins for a FinFET device. In one embodiment, dual strained channel layers are formed—a tensilely strained layer for NFET devices, and a compressively strained layer for PFET devices.
    Type: Application
    Filed: December 31, 2014
    Publication date: June 30, 2016
    Inventors: Pierre MORIN, Kangguo CHENG, Jody FRONHEISER, Xiuyu CAI, Juntao LI, Shogo MOCHIZUKI, Ruilong XIE, Hong HE, Nicolas LOUBET
  • Publication number: 20160181439
    Abstract: A field-effect transistor including an active zone comprises a source, a channel, a drain and a control gate, which is positioned level with the channel, allowing a current to flow through the channel between the source and drain along an x-axis, the channel comprising: a first edge of separation with the source; and a second edge of separation with the drain; the channel being compressively or tensilely strained, wherein the channel includes a localized perforation or a set of localized perforations along at least the first and/or second edge of the channel so as to also create at least one shear strain in the channel. A process for fabricating the transistor is provided.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 23, 2016
    Inventors: Emmanuel AUGENDRE, Maxime ARGOUD, Sylvain MAITREJEAN, Pierre MORIN, Raluca TIRON
  • Publication number: 20160172497
    Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 16, 2016
    Inventors: Nicolas LOUBET, Pierre MORIN
  • Publication number: 20160149037
    Abstract: Method of making at least one transistor strained channel semiconducting structure, comprising steps to form a sacrificial gate block and insulating spacers arranged in contact with the lateral faces of the sacrificial gate block, form sacrificial regions in contact with the lateral faces of said semiconducting zone, said sacrificial regions being configured so as to apply a strain on said semiconducting zone, remove said sacrificial gate block between said insulating spacers, replace said sacrificial gate block by a replacement gate block between said insulating spacers, remove said sacrificial regions, and replace said sacrificial regions by replacement regions in contact with the lateral faces of said semiconducting zone, on a semiconducting zone that will form a transistor channel region.
    Type: Application
    Filed: November 24, 2015
    Publication date: May 26, 2016
    Applicants: Commissariat a l'energie atomique et aux energies alternatives, STMICROELECTRONICS, Inc.
    Inventors: Shay REBOH, Pierre MORIN
  • Publication number: 20160133736
    Abstract: A static induction transistor is formed on a silicon carbide substrate doped with a first conductivity type. First recessed regions in a top surface of the silicon carbide substrate are filled with epitaxially grown gate regions in situ doped with a second conductivity type. Epitaxially grown channel regions in situ doped with the first conductivity type are positioned between adjacent epitaxial gate regions. Epitaxially grown source regions in situ doped with the first conductivity type are positioned on the epitaxial channel regions. The bottom surface of the silicon carbide substrate includes second recessed regions vertically aligned with the channel regions and silicided to support formation of the drain contact. The top surfaces of the source regions are silicided to support formation of the source contact. A gate lead is epitaxially grown and electrically coupled to the gate regions, with the gate lead silicided to support formation of the gate contact.
    Type: Application
    Filed: November 19, 2015
    Publication date: May 12, 2016
    Applicant: STMICROELECTRONICS, INC.
    Inventors: Pierre Morin, John Hongguang Zhang
  • Publication number: 20160133692
    Abstract: Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.
    Type: Application
    Filed: December 29, 2015
    Publication date: May 12, 2016
    Inventors: Pierre Morin, Maud Vinet, Laurent Grenouillet, Ajey Poovannummoottil Jacob
  • Patent number: 9331175
    Abstract: The disclosure concerns a method of stressing a semiconductor layer comprising: depositing, over a semiconductor on insulator (SOI) structure having a semiconductor layer in contact with an insulating layer, a stress layer; locally stressing said semiconductor layer by forming one or more openings in said stress layer, said openings being aligned with first regions of said semiconductor layer in which transistor channels are to be formed; and deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: May 3, 2016
    Assignees: STMicroelectronics SA, STMicroelectronics, Inc.
    Inventors: Pierre Morin, Denis Rideau, Olivier Nier
  • Publication number: 20160118497
    Abstract: Methods and structures for forming strained-channel FETs are described. A strain-inducing layer may be formed under stress in a silicon-on-insulator substrate below the insulator. Stress-relief cuts may be formed in the strain-inducing layer to relieve stress in the strain-inducing layer. The relief of stress can impart strain to an adjacent semiconductor layer. Strained-channel, fully-depleted SOI FETs and strained-channel finFETs may be formed from the adjacent semiconductor layer. The amount and type of strain may be controlled by etch depths and geometries of the stress-relief cuts and choice of materials for the strain-inducing layer.
    Type: Application
    Filed: December 21, 2015
    Publication date: April 28, 2016
    Inventor: Pierre Morin
  • Patent number: 9318372
    Abstract: One or more embodiments of the disclosure concerns a method of forming a stressed semiconductor layer involving: forming, in a surface of a semiconductor structure having a semiconductor layer in contact with an insulator layer, at least two first trenches in a first direction; introducing, via the at least two first trenches, a stress in the semiconductor layer and temporally decreasing, by annealing, the viscosity of the insulator layer; and extending the depth of the at least two first trenches to form first isolation trenches in the first direction delimiting a first dimension of at least one transistor to be formed in the semiconductor structure.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: April 19, 2016
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS, STMicroelectronics, Inc.
    Inventors: Olivier Nier, Denis Rideau, Pierre Morin, Emmanuel Josse
  • Publication number: 20160093639
    Abstract: A method for making a semiconductor device may include forming, on a first semiconductor layer of a semiconductor-on-insulator (SOI) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer. The method may further include performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer, and removing the second semiconductor layer.
    Type: Application
    Filed: December 10, 2015
    Publication date: March 31, 2016
    Inventors: PIERRE MORIN, QING LIU, NICOLAS LOUBET
  • Patent number: 9287130
    Abstract: A method includes forming a plurality of fin elements above a substrate. A mask is formed above the substrate. The mask has an opening defined above at least one selected fin element of the plurality of fin elements. An ion species is implanted into the at least one selected fin element through the opening to increase its etch characteristics relative to the other fin elements. The at least one selected fin element is removed selectively relative to the other fin elements.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: March 15, 2016
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation, STMicroelectronics, Inc.
    Inventors: Xiuyu Cai, Ajey Poovannummoottil Jacob, Ruilong Xie, Bruce Doris, Kangguo Cheng, Jason R. Cantone, Sylvie Mignot, David Moreau, Muthumanickam Sankarapandian, Pierre Morin, Su Chen Fan, Kisik Choi, Murat K. Akarvardar
  • Publication number: 20160064566
    Abstract: A method of making a semiconductor device includes forming a first spacer for at least one gate stack on a first semiconductor material layer, and forming a respective second spacer for each of source and drain regions adjacent the at least one gate. Each second spacer has a pair of opposing sidewalls and an end wall coupled thereto. The method includes filling the source and drain regions with a second semiconductor material while the first and second spacers provide confinement.
    Type: Application
    Filed: November 12, 2015
    Publication date: March 3, 2016
    Inventors: NICOLAS LOUBET, PIERRE MORIN
  • Patent number: 9269768
    Abstract: An insulation wall separating transistors formed in a thin semiconductor layer resting on an insulating layer laid on a semiconductor substrate, this wall being formed of an insulating material and comprising a wall crossing the thin layer and the insulating layer and penetrating into the substrate, and lateral extensions extending in the substrate under the insulating layer.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: February 23, 2016
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: David Barge, Pierre Morin
  • Publication number: 20160035820
    Abstract: Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.
    Type: Application
    Filed: July 31, 2014
    Publication date: February 4, 2016
    Applicants: STMicroelectronics, Inc., Commissariat a l'Energie Atomique et aux Energies Alternatives, GLOBALFOUNDRIES Inc.
    Inventors: Pierre Morin, Maud Vinet, Laurent Grenouillet, Ajey Poovannummoottil Jacob
  • Patent number: 9252208
    Abstract: Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: February 2, 2016
    Assignees: STMicroelectronics, Inc., Commissariat A L'Energie Atomique Et Aux Energies Alternives, GlobalFoundries Inc.
    Inventors: Pierre Morin, Maud Vinet, Laurent Grenouillet, Ajey Poovannummoottil Jacob
  • Patent number: 9245953
    Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: January 26, 2016
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Nicolas Loubet, Pierre Morin
  • Patent number: 9240466
    Abstract: The disclosure concerns a method of stressing a semiconductor layer comprising: forming, over a silicon on insulator structure having a semiconductor layer in contact with an insulating layer, one or more stressor blocks aligned with first regions of said semiconductor layer in which transistor channels are to be formed, wherein said stressor blocks are stressed such that they locally stress said semiconductor layer; and deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: January 19, 2016
    Assignees: STMicroelectronics SA, STMicroelectronics, Inc.
    Inventors: Pierre Morin, Denis Rideau, Olivier Nier
  • Patent number: 9236474
    Abstract: Methods and structures for forming strained-channel FETs are described. A strain-inducing layer may be formed under stress in a silicon-on-insulator substrate below the insulator. Stress-relief cuts may be formed in the strain-inducing layer to relieve stress in the strain-inducing layer. The relief of stress can impart strain to an adjacent semiconductor layer. Strained-channel, fully-depleted SOI FETs and strained-channel finFETs may be formed from the adjacent semiconductor layer. The amount and type of strain may be controlled by etch depths and geometries of the stress-relief cuts and choice of materials for the strain-inducing layer.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: January 12, 2016
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Pierre Morin
  • Patent number: 9236380
    Abstract: A method for making a semiconductor device may include forming, on a first semiconductor layer of a semiconductor-on-insulator (SOI) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer. The method may further include performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer, and removing the second semiconductor layer.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: January 12, 2016
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Pierre Morin, Qing Liu, Nicolas Loubet
  • Patent number: 9224845
    Abstract: A static induction transistor is formed on a silicon carbide substrate doped with a first conductivity type. First recessed regions in a top surface of the silicon carbide substrate are filled with epitaxially grown gate regions in situ doped with a second conductivity type. Epitaxially grown channel regions in situ doped with the first conductivity type are positioned between adjacent epitaxial gate regions. Epitaxially grown source regions in situ doped with the first conductivity type are positioned on the epitaxial channel regions. The bottom surface of the silicon carbide substrate includes second recessed regions vertically aligned with the channel regions and silicided to support formation of the drain contact. The top surfaces of the source regions are silicided to support formation of the source contact. A gate lead is epitaxially grown and electrically coupled to the gate regions, with the gate lead silicided to support formation of the gate contact.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: December 29, 2015
    Assignee: STMicroelectronics, Inc.
    Inventors: John Hongguang Zhang, Pierre Morin