Abstract: A method of making a semiconductor device includes forming a first spacer for at least one gate stack on a first semiconductor material layer, and forming a respective second spacer for each of source and drain regions adjacent the at least one gate. Each second spacer has a pair of opposing sidewalls and an end wall coupled thereto. The method includes filling the source and drain regions with a second semiconductor material while the first and second spacers provide confinement.

Abstract: Methods of fabricating semiconductor structures involve the formation of fins for finFET transistors having different stress/strain states. Fins of one stress/strain state may be employed to form n-type finFETS, while fins of another stress/strain state may be employed to form p-type finFETs. The fins having different stress/strain states may be fabricated from a common layer of semiconductor material. Semiconductor structures and devices are fabricated using such methods.

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

Abstract: Methods and structures for increasing strain in fully insulated finFETs are described. The finFET structures may be formed on an insulating layer and include source, channel, and drain regions that are insulated all around. During fabrication, the source and drain regions may be formed as suspended structures. A strain-inducing material may be formed around the source and drain regions on four contiguous sides so as to impart strain to the channel region of the finFET.

Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

Abstract: Methods and structures for increasing strain in fully insulated finFETs are described. The finFET structures may be formed on an insulating layer and include source, channel, and drain regions that are insulated all around. During fabrication, the source and drain regions may be formed as suspended structures. A strain-inducing material may be formed around the source and drain regions on four contiguous sides so as to impart strain to the channel region of the finFET.

Abstract: Methods and structures for forming a localized, strained region of a substrate are described. Trenches may be formed at boundaries of a localized region of a substrate. An upper portion of sidewalls at the localized region may be covered with a covering layer, and a lower portion of the sidewalls at the localized region may not be covered. A converting material may be formed in contact with the lower portion of the localized region, and the substrate heated. The heating may introduce a chemical species from the converting material into the lower portion, which creates stress in the localized region. The methods may be used to form strained-channel finFETs.

Abstract: Methods and structures for forming strained-channel FETs are described. A strain-inducing layer may be formed under stress in a silicon-on-insulator substrate below the insulator. Stress-relief cuts may be formed in the strain-inducing layer to relieve stress in the strain-inducing layer. The relief of stress can impart strain to an adjacent semiconductor layer. Strained-channel, fully-depleted SOI FETs and strained-channel finFETs may be formed from the adjacent semiconductor layer. The amount and type of strain may be controlled by etch depths and geometries of the stress-relief cuts and choice of materials for the strain-inducing layer.

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

Abstract: An insulation wall separating transistors formed in a thin semiconductor layer resting on an insulating layer laid on a semiconductor substrate, this wall being formed of an insulating material and comprising a wall crossing the thin layer and the insulating layer and penetrating into the substrate, and lateral extensions extending in the substrate under the insulating layer.

Abstract: The invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a semiconductor structure having a stressed semiconductor layer, one or more first isolation trenches in a first direction for delimiting a first dimension of at least one transistor to be formed in said semiconductor structure; forming, in the semiconductor structure, one or more second isolation trenches in a second direction for delimiting a second dimension of the at least one transistor, the first and second isolation trenches being at least partially filled with an insulating material; and before or after the formation of the second isolation trenches, decreasing the viscosity of the insulating material in the first isolation trenches by implanting atoms of a first material into the first isolation trenches, wherein atoms of the first material are not implanted into the second isolation trenches.

Abstract: One or more embodiments of the disclosure concerns a method of forming a stressed semiconductor layer involving: forming, in a surface of a semiconductor structure having a semiconductor layer in contact with an insulator layer, at least two first trenches in a first direction; introducing, via the at least two first trenches, a stress in the semiconductor layer and temporally decreasing, by annealing, the viscosity of the insulator layer; and extending the depth of the at least two first trenches to form first isolation trenches in the first direction delimiting a first dimension of at least one transistor to be formed in the semiconductor structure.

Abstract: A method for making a semiconductor device may include forming, on a first semiconductor layer of a semiconductor-on-insulator (SOI) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer. The method may further include performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer, and removing the second semiconductor layer.

Abstract: A method for forming a semiconductor device includes forming a mask layer on a stressed semiconductor layer of a stressed, semiconductor-on-insulator wafer. An isolation trench bounding the stressed semiconductor layer is formed. The isolation trench extends through the mask layer and into the SOI wafer past an oxide layer thereof. A dielectric body is formed in the isolation trench. A relaxation reduction liner is formed on the dielectric body and on an adjacent sidewall of the stressed semiconductor layer. The mask layer on the stressed semiconductor layer is removed.

Abstract: An apparatus of a semiconductor is provided wherein the apparatus comprises a substrate, a stack, and a fin. The substrate supports the stack and the substrate comprises a first material. The stack provides for the fin and the stack comprises: a strain induced in the stack via the substrate; the first material and a second material; and a plurality of concentrations of the second material with respect to the first material. The fin provides a source and a drain of a field effect transistor.

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

Abstract: The disclosure concerns a method of stressing a semiconductor layer comprising: forming, over a silicon on insulator structure having a semiconductor layer in contact with an insulating layer, one or more stressor blocks aligned with first regions of said semiconductor layer in which transistor channels are to be formed, wherein said stressor blocks are stressed such that they locally stress said semiconductor layer; and deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer.

Abstract: The disclosure concerns a method of stressing a semiconductor layer comprising: depositing, over a semiconductor on insulator (SOI) structure having a semiconductor layer in contact with an insulating layer, a stress layer; locally stressing said semiconductor layer by forming one or more openings in said stress layer, said openings being aligned with first regions of said semiconductor layer in which transistor channels are to be formed; and deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer.

Abstract: An insulation wall separating transistors formed in a thin semiconductor layer resting on an insulating layer laid on a semiconductor substrate, this wall being formed of an insulating material and comprising a wall crossing the thin layer and the insulating layer and penetrating into the substrate, and lateral extensions extending in the substrate under the insulating layer.